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mrsmond's library [79 articles]

Recent papers added to mrsmond's library.
  • Challenges and Solutions for Late- and Post-Silicon Design
    IEEE Design and Test of Computers, Vol. 25, No. 4. (2008), pp. 296-302.
    by Jan M Rabaey, Sharad Malik
    posted to trend silicon semiconductor review by mrsmond on 2008-08-06 12:12:43 as read
  • ESD: a pervasive reliability concern for IC technologies
    Proceedings of the IEEE, Vol. 81, No. 5. (1993), pp. 690-702.
    by C Duvvury, A Amerasekera
    posted to review reliability esd by mrsmond on 2008-08-05 16:49:59 as **
  • Copper metallization reliability
    Microelectronics Reliability, Vol. 39, No. 11. (November 1999), pp. 1595-1602.
    by JR Lloyd, J Clemens, R Snede
    posted to electromigration by mrsmond on 2008-08-05 16:22:00 as ***
  • Dilemmas in a General Theory of Planning
    Policy Sciences, Vol. 4 (1973), pp. 155-169.
    by Horst Rittel, Melvin Webber
    posted to theory planning design by mrsmond on 2008-06-19 11:17:21 as ****
  • Soft Error Mitigation Through Selective Addition of Functionally Redundant Wires
    Reliability, IEEE Transactions on, Vol. 57, No. 1. (2008), pp. 23-31.
    by S Almukhaizim, Y Makris
    posted to seu ser fault-injection combinational-logic circuit-level by mrsmond on 2008-04-24 16:59:37 as *
  • Fault injection for dependability validation: a methodology and some applications
    Software Engineering, IEEE Transactions on, Vol. 16, No. 2. (1990), pp. 166-182.
    by J Arlat, M Aguera, L Amat, Y Crouzet, JC Fabre, JC Laprie, E Martins, D Powell
    posted to verification fault-tolerance fault-injection dependability by mrsmond on 2008-04-24 16:26:37 as ** along with 1 person network01
  • DEPENDABLE COMPUTING AND FAULT TOLERANCE : CONCEPTS AND TERMINOLOGY
    Fault-Tolerant Computing, 1995, ' Highlights from Twenty-Five Years'., Twenty-Fifth International Symposium on (1995), 2.
    by JC Laprie
    posted to theory fault-tolerance dependability by mrsmond on 2008-04-24 16:02:44 as ** along with 1 person king_yous
  • Fault injection for formal testing of fault tolerance
    Reliability, IEEE Transactions on, Vol. 45, No. 3. (1996), pp. 443-455.
    by D Avresky, J Arlat, JC Laprie, Y Crouzet
    posted to off-chip-communication interesting--low formal-methods fault-tolerance fault-injection by mrsmond on 2008-04-24 15:53:20 as * along with 1 person network01
  • Evaluation of deterministic fault injection for fault-tolerant protocol testing
    Fault-Tolerant Computing, 1991. FTCS-21. Digest of Papers., Twenty-First International Symposium (1991), pp. 418-425.
    by K Echtle, Y Chen
    posted to off-chip-communication interesting--low fault-tolerance fault-injection by mrsmond on 2008-04-24 15:28:40 as * along with 1 person network01
  • Error analysis for the support of robust voltage scaling
    Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on (2005), pp. 65-70.
    by D Roberts, T Austin, D Blauww, T Mudge, K Flautner
    posted to dynamic-voltage-scaling energy-analysis have-paper-copy razor by mrsmond on 2008-04-04 14:40:56 as **
  • A robust self-calibrating transmission scheme for on-chip networks
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Vol. 13, No. 1. (2005), pp. 126-139.
    by F Worm, P Ienne, P Thiran, G De Micheli
    posted to dynamic-voltage-scaling energy-analysis on-chip-communication self-checking variability by mrsmond on 2008-04-04 14:38:03 as **
  • Making typical silicon matter with Razor
    Computer, Vol. 37, No. 3. (2004), pp. 57-65.
    by T Austin, D Blaauw, T Mudge, K Flautner
    posted to dynamic-voltage-scaling energy-analysis error-detection have-paper-copy razor variability by mrsmond on 2008-04-04 14:31:54 as **
  • DVS for on-chip bus designs based on timing error correction
    Design, Automation and Test in Europe, 2005. Proceedings (2005), pp. 80-85 Vol. 1.
    by H Kaul, D Sylvester, D Blaauw, T Mudge, T Austin
    posted to dynamic-voltage-scaling have-paper-copy on-chip-communication razor variability by mrsmond on 2008-04-04 14:29:30 as read
  • Transaction Level Error Susceptibility Model for Bus Based SoC Architectures
    (2006), pp. 775-780.
    by IC Lin, S Srinivasan, N Vijaykrishnan, N Dhanwada
    posted to amba arm fault-analysis have-paper-copy modeling on-chip-communication reliability system-level by mrsmond on 2008-02-25 16:04:47 as read
  • Watchdog processors in parallel systems
    Microprocess. Microprogram., Vol. 39, No. 2-5. (1993), pp. 69-74.
    by András Pataricza, István Majzik, Wolfgang Hohl, Joachim Hönig
    posted to error-detection have-paper-copy multiprocessor system-level by mrsmond on 2008-02-21 11:50:02 as *
  • Using formal techniques to debug the AMBA system-on-chip bus protocol
    Design, Automation and Test in Europe Conference and Exhibition, 2003 (2003), pp. 828-833.
    by A Roychoudhury, T Mitra, SR Karri
    posted to amba arm formal-methods on-chip-communication by mrsmond on 2008-02-08 15:31:43 as **
  • Formal performance evaluation of AMBA-based system-on-chip designs
    (2006), pp. 311-320.
    by Gabor Madl, Sudeep Pasricha, Luis, Nikil Dutt, Qiang Zhu
    posted to amba arm formal-methods on-chip-communication verification by mrsmond on 2008-02-08 15:26:44 as **
  • An AMBA-ARM7 Formal Verification Platform
    Formal Methods and Software Engineering (2003), pp. 48-67.
    by Kong Susanto, Tom Melham
    posted to amba arm formal-methods verification by mrsmond on 2008-02-08 15:17:30 as **
  • Verification of AMBA Using a Combination of Model Checking and Theorem Proving
    (2005)
    by Hasan Amjad
    posted to amba formal-methods modeling on-chip-communication verification by mrsmond on 2008-02-08 15:04:43 as **
  • Characterizing Logical Masking Of Transient Faults At The Microarchitectural And Architectural Levels
    by Nicholas Wang
    posted to combinational-logic cpu fault-analysis fault-injection microarchitecture toread transient-faults by mrsmond on 2008-01-08 12:37:05 as **
  • Latch Susceptibility to Transient Faults and New Hardening Approach
    IEEE Transactions on Computers, Vol. 56, No. 09. (2007), pp. 1255-1268.
    by Martin Omaña, Daniele Rossi, Cecilia Metra
    posted to circuit-level fault-detection fault-tolerance transient-faults by mrsmond on 2007-11-01 11:57:16 as **
  • A stimulus-free probabilistic model for single-event-upset sensitivity
    VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on (2006), 8 pp..
    by Thara Rejimon, Sanjukta Bhanja
    posted to modeling ser seu static by mrsmond on 2007-10-31 17:12:37 as **
  • An efficient static algorithm for computing the soft error rates of combinational circuits
    (2006), pp. 164-169.
    by Rajeev R Rao, Kaviraj Chopra, David Blaauw, Dennis Sylvester
    posted to combinational-logic modeling ser static by mrsmond on 2007-10-31 17:09:40 as ***
  • Communities of Interest
    Lecture Notes in Computer Science, Vol. 2189 (2001), pp. 105-??.
    by Corinna Cortes, Daryl Pregibon, Chris Volinsky
    posted to graph-theory by mrsmond on 2007-10-30 17:28:57 as ** along with 1 person elsantosneto
  • Single event upset in avionics
    Nuclear Science, IEEE Transactions on, Vol. 40, No. 2. (1993), pp. 120-126.
    by A Taber, E Normand
    posted to aerospace experiment seu by mrsmond on 2007-10-26 10:59:45 as **
  • Calculation of the soft error rate of submicron CMOS logic circuits
    Solid-State Circuits, IEEE Journal of, Vol. 30, No. 7. (1995), pp. 830-834.
    by T Juhnke, H Klar
    posted to circuit ser simulation trend by mrsmond on 2007-10-25 16:32:42 as **
  • Analysis of single-event effects in combinational logic-simulation of the AM2901 bitslice processor
    Nuclear Science, IEEE Transactions on, Vol. 47, No. 6. (2000), pp. 2609-2615.
    by LW Massengill, AE Baranski, DO Van Nort, J Meng, BL Bhuva
    posted to combinational-logic fault-analysis fault-injection ser simulation trend by mrsmond on 2007-10-25 16:30:05 as **
  • On latching probability of particle induced transients in combinational networks
    Fault-Tolerant Computing, 1994. FTCS-24. Digest of Papers., Twenty-Fourth International Symposium on (1994), pp. 340-349.
    by P Liden, P Dahlgren, R Johansson, J Karlsson
    posted to combinational-logic modeling seu by mrsmond on 2007-10-25 16:27:21 as **
  • Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
    IEEE Transactions on Dependable and Secure Computing, Vol. 01, No. 2. (2004), pp. 128-143.
    by Tanay Karnik, Peter Hazucha, Jagdish Patel
    posted to reliability review ser silicon-on-insulator by mrsmond on 2007-10-25 16:13:48 as **
  • ReStore: Symptom-Based Soft Error Detection in Microprocessors
    IEEE Transactions on Dependable and Secure Computing, Vol. 3, No. 3. (2006), pp. 188-201.
    by Nicholas J Wang, Sanjay J Patel
    posted to fault-tolerance simulation by mrsmond on 2007-10-25 16:08:12 as **
  • Modeling Soft Errors at Device and Logic Level for combinational circuits
    IEEE Transactions on Dependable and Secure Computing (September 2007)
    by Rajaraman Ramanarayanan, Vijay S Degalahal, Ramakrishnan Krishnan, Jungsub Kim, Vijaykrishnan Narayanan, Yuan Xie, Mary J Irwin, Kenan Unlu
    posted to combinational-logic modeling ser by mrsmond on 2007-10-25 16:05:42 as ****
  • Crosstalk- and SEU-Aware Networks on Chips
    IEEE Design & Test of Computers, Vol. 24, No. 04. (2007), pp. 340-350.
    by Arthur P Frantz, Maico Cassel, Fernanda L Kastensmidt, Érika Cota, Luigi Carro
    posted to crosstalk network-on-chip reliability seu by mrsmond on 2007-10-23 10:36:52 as ***
  • Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
    IEEE Design & Test of Computers, Vol. 24, No. 05. (2007), pp. 430-441.
    by Miloš Krsti, Eckhard Grass, Frank K Gürkaynak, Pascal Vivet
    posted to gals review by mrsmond on 2007-10-23 10:18:00 as ***
  • Impacts of front-end and middle-end process modifications on terrestrial soft error rate
    Device and Materials Reliability, IEEE Transactions on, Vol. 5, No. 3. (2005), pp. 382-396.
    by P Roche, G Gasiot
    posted to manufacture-process neutron ser silicon-on-insulator toread by mrsmond on 2007-10-10 14:50:58 as ***
  • Impact of Parameter Variations on Circuits and Microarchitecture
    IEEE Micro, Vol. 26, No. 6. (2006), pp. 30-39.
    by Osman S Unsal, James W Tschanz, Keith Bowman, Vivek De, Xavier Vera, Antonio Gonzalez, Oguz Ergin
    posted to have-paper-copy microarchitecture review variability by mrsmond on 2007-09-12 15:13:55 as **
  • An Efficient Algorithm for Discovering Frequent Subgraphs
    IEEE Transactions on Knowledge and Data Engineering, Vol. 16, No. 9. (September 2004), pp. 1038-1051.
    by Michihiro Kuramochi, George Karypis
    posted to graph-theory maths by mrsmond on 2007-08-30 17:44:09 as **
  • Variability and energy awareness: a microarchitecture-level perspective
    Design Automation Conference, 2005. Proceedings. 42nd (2005), pp. 11-16.
    by D Marculescu, E Talpes
    posted to circuit energy-analysis have-paper-copy modeling variability by mrsmond on 2007-08-24 13:47:46 as read
  • Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
    Solid-State Circuits, IEEE Journal of, Vol. 37, No. 2. (2002), pp. 183-190.
    by KA Bowman, SG Duvall, JD Meindl
    posted to circuit have-paper-copy modeling shrinking trend variability by mrsmond on 2007-08-24 13:38:22 as ***
  • notes Parameter variations and impact on circuits and microarchitecture
    Design Automation Conference, 2003. Proceedings (2003), pp. 338-342.
    by S Borkar, T Karnik, S Narendra, J Tschanz, A Keshavarzi, V De
    posted to circuit-level microarchitecture variability by mrsmond on 2007-08-24 13:34:28 as ** along with 1 person yushanchou
  • Basic Concepts in Quantum Circuits (Tutorial)
    Design Automation Conference, Vol. 40 (June 2003)
    by John P Hayes
    posted to quantum-computing tutorial by mrsmond on 2007-08-24 13:30:40 as **
  • Design and reliability challenges in nanometer technologies
    Design Automation Conference, 2004. Proceedings. 41st (2004), pp. 75-75.
    by S Borkar, T Karnik, Vivek De
    posted to microarchitecture variability by mrsmond on 2007-08-24 12:07:41 as ***
  • Load and logic co-optimization for design of soft-error resistant nanometer CMOS circuits
    On-Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International (2005), pp. 35-40.
    by YS Dhillon, AU Diril, A Chatterjee, C Metra
    posted to combinational-logic energy-analysis fault-analysis fault-tolerance toread transient-faults by mrsmond on 2007-07-05 14:35:54 as ***
  • On transistor level gate sizing for increased robustness to transient faults
    On-Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International (2005), pp. 23-28.
    by JM Cazeaux, D Rossi, M Omana, C Metra, A Chatterjee
    posted to circuit-level fault-avoidance transient-faults by mrsmond on 2007-07-05 11:29:06 as **
  • Analyzing the effectiveness of fault hardening procedures
    On-Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International (2005), pp. 14-19.
    by P Gawkowski, J Sosnowski, B Radko
    posted to error-correction error-detection fault-avoidance software-level by mrsmond on 2007-07-05 11:26:39 as **
  • Analytical semi-empirical model for SER sensitivity estimation of deep-submicron CMOS circuits
    On-Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International (2005), pp. 3-8.
    by T Heijmen
    posted to ser simulation theory trend by mrsmond on 2007-07-05 11:24:41 as **
  • Error correction in arithmetic operations by I/O inversion
    On-Line Testing Symposium, 2006. IOLTS 2006. 12th IEEE International (2006), 6 pp..
    by P Oikonomakos, P Fox
    posted to architecture error-detection toread by mrsmond on 2007-07-05 11:22:15 as ***
  • Soft error rates in deep-submicron CMOS technologies
    On-Line Testing Symposium, 2006. IOLTS 2006. 12th IEEE International (2006), 1 pp..
    by T Heijmen
    posted to ser toread trend by mrsmond on 2007-07-05 11:19:01 as *** along with 1 person Pepijn
  • Real time fault injection using a modified debugging infrastructure
    On-Line Testing Symposium, 2006. IOLTS 2006. 12th IEEE International (2006), 6 pp..
    by AV Fidalgo, GR Alves, JM Ferreira
    posted to debug fault-injection system-level toread by mrsmond on 2007-07-05 11:17:19 as *** along with 1 person network01
  • Fault-robust microcontrollers for automotive applications
    On-Line Testing Symposium, 2006. IOLTS 2006. 12th IEEE International (2006), 6 pp..
    by R Mariani, P Fuhrmann, B Vittorelli
    posted to automotive fault-tolerance microcontroller system-level toread by mrsmond on 2007-07-05 11:13:00 as ***
  • DMT and DT2: two fault-tolerant architectures developed by CNES for COTS-based spacecraft supercomputers
    On-Line Testing Symposium, 2006. IOLTS 2006. 12th IEEE International (2006), 10 pp..
    by M Pignol
    posted to aerospace fault-tolerance super-computing system-level toread by mrsmond on 2007-07-05 11:09:22 as ***
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