On-line fault detection for bus-based field programmable gate arrays Export

@article{citeulike:1177531, abstract = {We introduce a technique for on-line built-in self-testing (BIST) of bus-based field programmable gate arrays (FPGAs). This system detects deviations from the intended functionality of an FPGA without using special-purpose hardware, hardware external to the device, and without interrupting system operation. Such a system would be useful for mission-critical applications with resource constraints. The system solves these problems through an on-line fault scanning methodology. A device's internal resources are configured to test for faults. Testing scans across an FPGA, checking a section at a time. Simulation on a model FPGA supports the viability and effectiveness of such a system}, author = {Shnidman, N. R. and Mangione-Smith, W. H. and Potkonjak, M.}, citeulike-article-id = {1177531}, citeulike-linkout-0 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=736139}, journal = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on}, keywords = {design-for-test, fault-detection, fault-tolerance, fpga, prj--fabric-reliability, simulation}, number = {4}, pages = {656--666}, posted-at = {2007-03-20 14:11:29}, priority = {2}, title = {On-line fault detection for bus-based field programmable gate arrays}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=736139}, volume = {6}, year = {1998} }

TY - JOUR ID - citeulike:1177531 L3 - citeulike-article-id:1177531 N2 - We introduce a technique for on-line built-in self-testing (BIST) of bus-based field programmable gate arrays (FPGAs). This system detects deviations from the intended functionality of an FPGA without using special-purpose hardware, hardware external to the device, and without interrupting system operation. Such a system would be useful for mission-critical applications with resource constraints. The system solves these problems through an on-line fault scanning methodology. A device's internal resources are configured to test for faults. Testing scans across an FPGA, checking a section at a time. Simulation on a model FPGA supports the viability and effectiveness of such a system IS - 4 JF - Very Large Scale Integration (VLSI) Systems, IEEE Transactions on EP - 666 TI - On-line fault detection for bus-based field programmable gate arrays VL - 6 SP - 656 KW - design-for-test KW - fault-detection KW - fault-tolerance KW - fpga KW - prj--fabric-reliability KW - simulation AU - Shnidman, NR AU - Mangione-Smith, WH AU - Potkonjak, M PY - 1998/// UR - http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=736139 ER -