Probabilistic maximum error modeling for unreliable logic circuits Export

by: Karthikeyan Lingasubramanian, Sanjukta Bhanja

In GLSVLSI '07: Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI (2007), pp. 223-226.

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@inproceedings{citeulike:1397320, address = {New York, NY, USA}, author = {Lingasubramanian, Karthikeyan and Bhanja, Sanjukta}, booktitle = {GLSVLSI '07: Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI}, citeulike-article-id = {1397320}, citeulike-linkout-0 = {http://portal.acm.org/citation.cfm?id=1228842}, citeulike-linkout-1 = {http://dx.doi.org/10.1145/1228784.1228842}, doi = {10.1145/1228784.1228842}, isbn = {9781595936059}, keywords = {error, modeling, reliability}, pages = {223--226}, posted-at = {2007-06-18 17:44:55}, priority = {2}, publisher = {ACM Press}, title = {Probabilistic maximum error modeling for unreliable logic circuits}, url = {http://dx.doi.org/10.1145/1228784.1228842}, year = {2007} }

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Probabilistic maximum error modeling for unreliable logic circuits Export

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