Fault tolerant system design method based on self-checking circuits Export

@inproceedings{citeulike:1436362, abstract = {This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults.}, author = {Kubalik, P. and Fiser, P. and Kubatova, H.}, citeulike-article-id = {1436362}, citeulike-linkout-0 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1655543}, journal = {On-Line Testing Symposium, 2006. IOLTS 2006. 12th IEEE International}, keywords = {circuit, fault-tolerance, fpga, self-checking, system-level, toread}, pages = {2 pp.+}, posted-at = {2007-07-05 11:00:37}, priority = {3}, title = {Fault tolerant system design method based on self-checking circuits}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1655543}, year = {2006} }

TY - CONF ID - citeulike:1436362 L3 - citeulike-article-id:1436362 N2 - This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults. JF - On-Line Testing Symposium, 2006. IOLTS 2006. 12th IEEE International TI - Fault tolerant system design method based on self-checking circuits SP - 2 pp. KW - circuit KW - fault-tolerance KW - fpga KW - self-checking KW - system-level KW - toread AU - Kubalik, P AU - Fiser, P AU - Kubatova, H PY - 2006/// UR - http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1655543 ER -