Error correction in arithmetic operations by I/O inversion Export

@proceedings{citeulike:1436479, abstract = {In this paper we demonstrate how error-correcting addition and multiplication can be performed using self-checking modules. Our technique is based on the observation that a suitably designed full adder under the presence of any single stuck-at fault produces the fault-free complement of the desired output when fed by the complement of its functional input. We initially apply conventional parity-based error detection in arithmetic modules; upon detection of a fault, this is followed by input inversion, recomputation, and suitable output inversion. We present adder, register and multiplier designs that can be used in this context. We also design a large-scale circuit using this technique (an elliptical filter), outlining the area savings with respect to traditional triple modular redundancy.}, author = {Oikonomakos, P. and Fox, P.}, citeulike-article-id = {1436479}, citeulike-linkout-0 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1655563}, journal = {On-Line Testing Symposium, 2006. IOLTS 2006. 12th IEEE International}, keywords = {architecture, error-detection, toread}, pages = {6 pp.+}, posted-at = {2007-07-05 11:22:15}, priority = {3}, title = {Error correction in arithmetic operations by I/O inversion}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1655563}, year = {2006} }

TY - CONF ID - citeulike:1436479 L3 - citeulike-article-id:1436479 N2 - In this paper we demonstrate how error-correcting addition and multiplication can be performed using self-checking modules. Our technique is based on the observation that a suitably designed full adder under the presence of any single stuck-at fault produces the fault-free complement of the desired output when fed by the complement of its functional input. We initially apply conventional parity-based error detection in arithmetic modules; upon detection of a fault, this is followed by input inversion, recomputation, and suitable output inversion. We present adder, register and multiplier designs that can be used in this context. We also design a large-scale circuit using this technique (an elliptical filter), outlining the area savings with respect to traditional triple modular redundancy. JF - On-Line Testing Symposium, 2006. IOLTS 2006. 12th IEEE International TI - Error correction in arithmetic operations by I/O inversion SP - 6 pp. KW - architecture KW - error-detection KW - toread AU - Oikonomakos, P AU - Fox, P PY - 2006/// UR - http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1655563 ER -