Load and logic co-optimization for design of soft-error resistant nanometer CMOS circuits Export

@inproceedings{citeulike:1436887, abstract = {Technology scaling has led to reduced noise margins and increased susceptibility of logic circuits to transient errors. In this paper, a novel methodology to increase the robustness of combinational circuits to transient errors is proposed. The number of errors propagated to the primary outputs (POs) is minimized by adding optimal amounts of capacitive loading to the POs of the logic circuit. Using a novel delay-assignment-variation (DAV) based optimization methodology, the sizes, supply voltages and threshold voltages of internal gates (not primary outputs) are chosen to minimize the energy and delay overhead due to the added loads. Experiments on ISCAS'85 benchmarks show that 79.3\% soft-error reduction can be obtained on the average with modest increase in circuit delay and energy. Comparison with other techniques shows that our technique has a much better energy-delay-reliability trade-off compared to others.}, author = {Dhillon, Y. S. and Diril, A. U. and Chatterjee, A. and Metra, C.}, citeulike-article-id = {1436887}, citeulike-linkout-0 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1498126}, journal = {On-Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International}, keywords = {combinational-logic, energy-analysis, fault-analysis, fault-tolerance, toread, transient-faults}, pages = {35--40}, posted-at = {2007-07-05 14:35:54}, priority = {3}, title = {Load and logic co-optimization for design of soft-error resistant nanometer CMOS circuits}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1498126}, year = {2005} }

TY - CONF ID - citeulike:1436887 L3 - citeulike-article-id:1436887 N2 - Technology scaling has led to reduced noise margins and increased susceptibility of logic circuits to transient errors. In this paper, a novel methodology to increase the robustness of combinational circuits to transient errors is proposed. The number of errors propagated to the primary outputs (POs) is minimized by adding optimal amounts of capacitive loading to the POs of the logic circuit. Using a novel delay-assignment-variation (DAV) based optimization methodology, the sizes, supply voltages and threshold voltages of internal gates (not primary outputs) are chosen to minimize the energy and delay overhead due to the added loads. Experiments on ISCAS'85 benchmarks show that 79.3% soft-error reduction can be obtained on the average with modest increase in circuit delay and energy. Comparison with other techniques shows that our technique has a much better energy-delay-reliability trade-off compared to others. JF - On-Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International EP - 40 TI - Load and logic co-optimization for design of soft-error resistant nanometer CMOS circuits SP - 35 KW - combinational-logic KW - energy-analysis KW - fault-analysis KW - fault-tolerance KW - toread KW - transient-faults AU - Dhillon, YS AU - Diril, AU AU - Chatterjee, A AU - Metra, C PY - 2005/// UR - http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1498126 ER -