Variability and energy awareness: a microarchitecture-level perspective Export

@proceedings{citeulike:1588656, abstract = {This paper proposes microarchitecture-level models for within die (WID) process and system parameter variability that can be included in the design of high-performance processors. Since decisions taken at microarchitecture level have the largest impact on both performance and power, on one hand, and global variability effect, on the other hand, models and associated metrics are needed for their joint characterization and analysis. To assess how these variations affect or are affected by microarchitecture decisions, we propose a joint performance, power and variability metric that is able to distinguish among various design choices. As a design-driver for the modeling methodology, we consider a clustered high-performance processor implementation, along with its globally asynchronous, locally synchronous (GALS) counterpart. Results show that, when comparing the baseline, synchronous and its GALS counterpart, microarchitecture-driven impact of process variability translates into 2-10\% faster local clocks for the GALS case, while when taking into account the effect of on-chip temperature variability, local clocks can be 8-18\% faster. If, in addition, voltage scaling (DVS) is employed, the GALS architecture with DVS is 26\% better in terms of the joint quality metric employing energy, performance, and variability.}, author = {Marculescu, D. and Talpes, E.}, booktitle = {Design Automation Conference, 2005. Proceedings. 42nd}, citeulike-article-id = {1588656}, citeulike-linkout-0 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1510283}, journal = {Design Automation Conference, 2005. Proceedings. 42nd}, keywords = {circuit, energy-analysis, have-paper-copy, modeling, variability}, pages = {11--16}, posted-at = {2007-08-24 13:47:46}, priority = {0}, title = {Variability and energy awareness: a microarchitecture-level perspective}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1510283}, year = {2005} }

TY - CONF ID - citeulike:1588656 L3 - citeulike-article-id:1588656 N2 - This paper proposes microarchitecture-level models for within die (WID) process and system parameter variability that can be included in the design of high-performance processors. Since decisions taken at microarchitecture level have the largest impact on both performance and power, on one hand, and global variability effect, on the other hand, models and associated metrics are needed for their joint characterization and analysis. To assess how these variations affect or are affected by microarchitecture decisions, we propose a joint performance, power and variability metric that is able to distinguish among various design choices. As a design-driver for the modeling methodology, we consider a clustered high-performance processor implementation, along with its globally asynchronous, locally synchronous (GALS) counterpart. Results show that, when comparing the baseline, synchronous and its GALS counterpart, microarchitecture-driven impact of process variability translates into 2-10% faster local clocks for the GALS case, while when taking into account the effect of on-chip temperature variability, local clocks can be 8-18% faster. If, in addition, voltage scaling (DVS) is employed, the GALS architecture with DVS is 26% better in terms of the joint quality metric employing energy, performance, and variability. JF - Design Automation Conference, 2005. Proceedings. 42nd EP - 16 TI - Variability and energy awareness: a microarchitecture-level perspective T2 - Design Automation Conference, 2005. Proceedings. 42nd SP - 11 KW - circuit KW - energy-analysis KW - have-paper-copy KW - modeling KW - variability AU - Marculescu, D AU - Talpes, E PY - 2005/// UR - http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1510283 ER -