Characterizing Logical Masking Of Transient Faults At The Microarchitectural And Architectural Levels

@misc{citeulike:2207607, abstract = {In this work, the e\#ects of transient faults on high performance microprocessors is explored. To perform a thorough exploration, a highly detailed RTL model of a modern, deeply pipelined, out-of-order microprocessor implementing the Alpha ISA was created. Using this model, the e\#ects of manipulating individual state elements such as pipeline latches and RAM cells can be observed by comparing the results against that of a reference simulation. Using statistical fault injection into our...}, author = {Wang, Nicholas}, citeulike-article-id = {2207607}, keywords = {combinational-logic, cpu, fault-analysis, fault-injection, microarchitecture, toread, transient-faults}, posted-at = {2008-01-08 12:37:05}, priority = {2}, title = {Characterizing Logical Masking Of Transient Faults At The Microarchitectural And Architectural Levels}, url = {http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.3.5554} }

TY - GEN ID - citeulike:2207607 L3 - citeulike-article-id:2207607 N2 - In this work, the e#ects of transient faults on high performance microprocessors is explored. To perform a thorough exploration, a highly detailed RTL model of a modern, deeply pipelined, out-of-order microprocessor implementing the Alpha ISA was created. Using this model, the e#ects of manipulating individual state elements such as pipeline latches and RAM cells can be observed by comparing the results against that of a reference simulation. Using statistical fault injection into our... TI - Characterizing Logical Masking Of Transient Faults At The Microarchitectural And Architectural Levels KW - combinational-logic KW - cpu KW - fault-analysis KW - fault-injection KW - microarchitecture KW - toread KW - transient-faults AU - Wang, Nicholas UR - http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.3.5554 ER -