Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits Export

@proceedings{citeulike:3360702, abstract = {This paper describes a tunable transient filter (TTF) design for soft error rate reduction in combinational logic circuits. TTFs can be inserted into combinational circuits to suppress propagated single- event upsets (SEUs) before they can be captured in latches/flip- flops. TTFs are tuned by adjusting the maximum width of the propagated SEU that can be suppressed. TTFs require 6-14 transistors, making them an attractive cost-effective option to reduce the soft error rate in combinational circuits. A global optimization approach based on geometric programming that integrates TTF insertion with dual-VoD and gate sizing is described. Simulation results for the 70 nm process technology indicate that a 17-48X reduction in the soft error rate can be achieved with this approach.}, author = {Zhou, Quming and Choudhury, M. R. and Mohanram, K.}, booktitle = {European Test, 2008 13th}, citeulike-article-id = {3360702}, citeulike-linkout-0 = {http://doi.ieeecomputersociety.org/10.1109/ETS.2008.39}, citeulike-linkout-1 = {http://dx.doi.org/10.1109/ETS.2008.39}, citeulike-linkout-2 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4556045}, doi = {10.1109/ETS.2008.39}, journal = {European Test, 2008 13th}, keywords = {circuit-level, fault-avoidance, seu}, pages = {179--184}, posted-at = {2009-04-01 12:18:05}, priority = {1}, title = {Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits}, url = {http://dx.doi.org/10.1109/ETS.2008.39}, year = {2008} }

TY - CONF ID - citeulike:3360702 L3 - citeulike-article-id:3360702 N2 - This paper describes a tunable transient filter (TTF) design for soft error rate reduction in combinational logic circuits. TTFs can be inserted into combinational circuits to suppress propagated single- event upsets (SEUs) before they can be captured in latches/flip- flops. TTFs are tuned by adjusting the maximum width of the propagated SEU that can be suppressed. TTFs require 6-14 transistors, making them an attractive cost-effective option to reduce the soft error rate in combinational circuits. A global optimization approach based on geometric programming that integrates TTF insertion with dual-VoD and gate sizing is described. Simulation results for the 70 nm process technology indicate that a 17-48X reduction in the soft error rate can be achieved with this approach. JF - European Test, 2008 13th EP - 184 TI - Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits T2 - European Test, 2008 13th SP - 179 KW - circuit-level KW - fault-avoidance KW - seu AU - Zhou, Quming AU - Choudhury, MR AU - Mohanram, K PY - 2008/// UR - http://dx.doi.org/10.1109/ETS.2008.39 ER -