Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS Export

@proceedings{citeulike:3585879, abstract = {With each technology node shrink, a silicon chip becomes more susceptible to soft errors. The susceptibility further increases as the voltage is scaled down to save energy. Based on analysis on cells from commercial libraries, we have quantified the increase in the soft error probability across 65nm and 45nm technology nodes at different supply voltages using the Qcrit based simulation methodology. The Qcrit for both bit cells and latches decreases by \~{}30\&\#x025; as the designs are scaled from 65nm to 45nm. This decrease is expected to continue with further technology scaling as well. The results show that at nominal voltage, the Qcrit for a latch is just \~{}20\&\#x025; more than that of the bit cell in sub-65nm technology nodes. Further, as the voltage is scaled from 1V to 0.4V, Qcrit decreases by \~{}5X which substantially increases the probability of an upset if a particle strike happens. This work shows that in sub-65nm technology nodes with aggressive voltage scaling, it is equally critical to solve the soft error problems in logic (latches, flip-flops) as it is in SRAMs.}, author = {Chandra, Vikas and Aitken, Robert}, booktitle = {Defect and Fault Tolerance of VLSI Systems, 2008. DFTVS '08. IEEE International Symposium on}, citeulike-article-id = {3585879}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/DFT.2008.50}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4641164}, doi = {10.1109/DFT.2008.50}, journal = {Defect and Fault Tolerance of VLSI Systems, 2008. DFTVS '08. IEEE International Symposium on}, keywords = {arm, circuit-level, modeling, ser, trend}, pages = {114--122}, posted-at = {2008-11-20 12:35:57}, priority = {3}, title = {Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS}, url = {http://dx.doi.org/10.1109/DFT.2008.50}, year = {2008} }

TY - CONF ID - citeulike:3585879 L3 - citeulike-article-id:3585879 N2 - With each technology node shrink, a silicon chip becomes more susceptible to soft errors. The susceptibility further increases as the voltage is scaled down to save energy. Based on analysis on cells from commercial libraries, we have quantified the increase in the soft error probability across 65nm and 45nm technology nodes at different supply voltages using the Qcrit based simulation methodology. The Qcrit for both bit cells and latches decreases by ~30% as the designs are scaled from 65nm to 45nm. This decrease is expected to continue with further technology scaling as well. The results show that at nominal voltage, the Qcrit for a latch is just ~20% more than that of the bit cell in sub-65nm technology nodes. Further, as the voltage is scaled from 1V to 0.4V, Qcrit decreases by ~5X which substantially increases the probability of an upset if a particle strike happens. This work shows that in sub-65nm technology nodes with aggressive voltage scaling, it is equally critical to solve the soft error problems in logic (latches, flip-flops) as it is in SRAMs. JF - Defect and Fault Tolerance of VLSI Systems, 2008. DFTVS '08. IEEE International Symposium on EP - 122 TI - Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS T2 - Defect and Fault Tolerance of VLSI Systems, 2008. DFTVS '08. IEEE International Symposium on SP - 114 KW - arm KW - circuit-level KW - modeling KW - ser KW - trend AU - Chandra, Vikas AU - Aitken, Robert PY - 2008/// UR - http://dx.doi.org/10.1109/DFT.2008.50 ER -