Selective Hardening in Early Design Steps Export

@inproceedings{citeulike:4252669, abstract = {Hardening a circuit against soft errors should be performed in early design steps before the circuit is laid out. A viable approach to achieve soft error rate (SER) reduction at a reasonable cost is to harden only parts of a circuit. When selecting which locations in the circuit to harden, priority should be given to critical spots for which an error is likely to cause a system malfunction. The criticality of the spots depends on parameters not all available in early design steps. We employ a selection strategy which takes only gate-level information into account and does not use any low-level electrical or timing information. We validate the quality of the solution using an accurate SER estimator based on the new UGC particle strike model. Although only partial information is utilized for hardening, the exact validation shows that the susceptibility of a circuit to soft errors is reduced significantly. The results of the hardening strategy presented are also superior to known purely topological strategies in terms of both hardware overhead and protection.}, author = {Zoellin, C. G. and Wunderlich, H. J. and Polian, I. and Becker, B.}, booktitle = {European Test, 2008 13th}, citeulike-article-id = {4252669}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/ETS.2008.30}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4556046}, doi = {10.1109/ETS.2008.30}, journal = {European Test, 2008 13th}, keywords = {circuit-level, fault-avoidance, seu}, pages = {185--190}, posted-at = {2009-04-01 12:02:11}, priority = {1}, title = {Selective Hardening in Early Design Steps}, url = {http://dx.doi.org/10.1109/ETS.2008.30}, year = {2008} }

TY - CONF ID - citeulike:4252669 L3 - citeulike-article-id:4252669 N2 - Hardening a circuit against soft errors should be performed in early design steps before the circuit is laid out. A viable approach to achieve soft error rate (SER) reduction at a reasonable cost is to harden only parts of a circuit. When selecting which locations in the circuit to harden, priority should be given to critical spots for which an error is likely to cause a system malfunction. The criticality of the spots depends on parameters not all available in early design steps. We employ a selection strategy which takes only gate-level information into account and does not use any low-level electrical or timing information. We validate the quality of the solution using an accurate SER estimator based on the new UGC particle strike model. Although only partial information is utilized for hardening, the exact validation shows that the susceptibility of a circuit to soft errors is reduced significantly. The results of the hardening strategy presented are also superior to known purely topological strategies in terms of both hardware overhead and protection. JF - European Test, 2008 13th EP - 190 TI - Selective Hardening in Early Design Steps T2 - European Test, 2008 13th SP - 185 KW - circuit-level KW - fault-avoidance KW - seu AU - Zoellin, CG AU - Wunderlich, HJ AU - Polian, I AU - Becker, B PY - 2008/// UR - http://dx.doi.org/10.1109/ETS.2008.30 ER -