Reducing power consumption in memory ECC checkers Export

@inproceedings{citeulike:4284648, abstract = {A method is proposed for reducing power consumption in memory ECC checker circuitry that provides SEC-DED. The degrees of freedom in selecting the parity check matrix are used to minimize power with little or no impact on area and delay. The power minimization method is applied to two popular SEC-DED codes: standard Hamming codes and odd-column-weight Hsiao codes. Experiments on actual memory traces of Spec and MediaBench benchmarks indicate that considering power in addition to area and delay when selecting the parity check matrix can result in power reductions of up to 27\% for Hsiao codes and up to 41\% for Hamming codes.}, author = {Ghosh, S. and Basu, S. and Touba, N. A.}, booktitle = {Test Conference, 2004. Proceedings. ITC 2004. International}, citeulike-article-id = {4284648}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/TEST.2004.1387407}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1387407}, comment = {PDF here has a few refs that might be useful: http://www.csl.sri.com/users/shalini/low-power-ced-jolpe05.pdf}, doi = {10.1109/TEST.2004.1387407}, journal = {Test Conference, 2004. Proceedings. ITC 2004. International}, keywords = {energy-analysis, error-correction, memory}, pages = {1322--1331}, posted-at = {2009-04-07 17:40:53}, priority = {2}, title = {Reducing power consumption in memory ECC checkers}, url = {http://dx.doi.org/10.1109/TEST.2004.1387407}, year = {2004} }

TY - CONF ID - citeulike:4284648 L3 - citeulike-article-id:4284648 N2 - A method is proposed for reducing power consumption in memory ECC checker circuitry that provides SEC-DED. The degrees of freedom in selecting the parity check matrix are used to minimize power with little or no impact on area and delay. The power minimization method is applied to two popular SEC-DED codes: standard Hamming codes and odd-column-weight Hsiao codes. Experiments on actual memory traces of Spec and MediaBench benchmarks indicate that considering power in addition to area and delay when selecting the parity check matrix can result in power reductions of up to 27% for Hsiao codes and up to 41% for Hamming codes. JF - Test Conference, 2004. Proceedings. ITC 2004. International EP - 1331 TI - Reducing power consumption in memory ECC checkers T2 - Test Conference, 2004. Proceedings. ITC 2004. International SP - 1322 KW - energy-analysis KW - error-correction KW - memory N1 - PDF here has a few refs that might be useful: http://www.csl.sri.com/users/shalini/low-power-ced-jolpe05.pdf AU - Ghosh, S AU - Basu, S AU - Touba, NA PY - 2004/// UR - http://dx.doi.org/10.1109/TEST.2004.1387407 ER -