Assertion-Based Microarchitecture Design for Improved Fault Tolerance Export

@inproceedings{citeulike:6092969, abstract = {Protection against transient faults is an important constraint in high-performance processor design. One strategy for achieving efficient reliability is to apply targeted fault checking/masking techniques to different units within an overall reliability regimen. In this spirit, we propose a novel class of targeted fault checks that verify the functioning of the microarchitecture itself, as opposed to the broader challenge of verifying overall architectural correctness of a running program. That is, the checks focus on verifying the mechanics of executing the program. Long term, discriminating between machinery and state may lead to highly efficient reliability solutions with high coverage. The key idea is to identify and exploit opportunities to assert microarchitectural "truths". We explore two examples, Register Name Authentication (RNA) for the rename unit and Timestamp-Based Assertion Checking (TAC) for the issue unit of a contemporary out-of-order superscalar processor. Thousands of fault injection experiments show that RNA and TAC microarchitectural assertions detect most unmasked faults for which they are designed.}, author = {Reddv, V. K. and Al-Zawawi, A. S. and Rotenberg, E.}, citeulike-article-id = {6092969}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/ICCD.2006.4380842}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4380842}, day = {12}, doi = {10.1109/ICCD.2006.4380842}, journal = {Computer Design, 2006. ICCD 2006. International Conference on}, keywords = {fault-detection, fault-injection, fault-tolerance, microarchitecture, transient-faults}, month = {November}, pages = {362--369}, posted-at = {2009-11-10 12:25:02}, priority = {0}, title = {Assertion-Based Microarchitecture Design for Improved Fault Tolerance}, url = {http://dx.doi.org/10.1109/ICCD.2006.4380842}, year = {2007} }

TY - CONF ID - citeulike:6092969 L3 - citeulike-article-id:6092969 N2 - Protection against transient faults is an important constraint in high-performance processor design. One strategy for achieving efficient reliability is to apply targeted fault checking/masking techniques to different units within an overall reliability regimen. In this spirit, we propose a novel class of targeted fault checks that verify the functioning of the microarchitecture itself, as opposed to the broader challenge of verifying overall architectural correctness of a running program. That is, the checks focus on verifying the mechanics of executing the program. Long term, discriminating between machinery and state may lead to highly efficient reliability solutions with high coverage. The key idea is to identify and exploit opportunities to assert microarchitectural "truths". We explore two examples, Register Name Authentication (RNA) for the rename unit and Timestamp-Based Assertion Checking (TAC) for the issue unit of a contemporary out-of-order superscalar processor. Thousands of fault injection experiments show that RNA and TAC microarchitectural assertions detect most unmasked faults for which they are designed. JF - Computer Design, 2006. ICCD 2006. International Conference on EP - 369 TI - Assertion-Based Microarchitecture Design for Improved Fault Tolerance SP - 362 KW - fault-detection KW - fault-injection KW - fault-tolerance KW - microarchitecture KW - transient-faults AU - Reddv, VK AU - Al-Zawawi, AS AU - Rotenberg, E PY - 2007/11/12/ UR - http://dx.doi.org/10.1109/ICCD.2006.4380842 ER -