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mrsmond's Dhillon:YS [2 articles] Export Sort

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	Soft-error tolerance analysis and optimization of nanometer circuits [My Copy] In Design, Automation and Test in Europe, 2005. Proceedings (2005) by Y. S. Dhillon, A. U. Diril, A. Chatterjee posted to jabref-file-import-09-05-08 by mrsmond on 2009-05-08 16:55:47 as
	Load and logic co-optimization for design of soft-error resistant nanometer CMOS circuits [My Copy] On-Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International (2005), pp. 35-40. by Y. S. Dhillon, A. U. Diril, A. Chatterjee, C. Metra posted to combinational-logic energy-analysis fault-analysis fault-tolerance toread transient-faults by mrsmond on 2007-07-05 14:35:54 as