mrsmond's combinational-logic [12 articles] Export

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	Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits [My Copy] European Test Symposium, IEEE, Vol. 0 (2008), pp. 179-184. by Quming Zhou, Mihir R. Choudhury, Kartik Mohanram posted to circuit-level combinational-logic fault-avoidance transient-faults interesting-rating--2 by mrsmond on 2008-09-30 12:18:50 as
	Soft Error Mitigation Through Selective Addition of Functionally Redundant Wires [My Copy] Reliability, IEEE Transactions on In Reliability, IEEE Transactions on, Vol. 57, No. 1. (2008), pp. 23-31. by S. Almukhaizim, Y. Makris posted to circuit-level combinational-logic fault-injection ser seu by mrsmond on 2008-04-24 16:59:37 as
	Characterizing Logical Masking Of Transient Faults At The Microarchitectural And Architectural Levels [My Copy] by Nicholas Wang posted to combinational-logic cpu fault-analysis fault-injection microarchitecture toread transient-faults by mrsmond on 2008-01-08 12:37:05 as
	An efficient static algorithm for computing the soft error rates of combinational circuits [My Copy] In DATE '06: Proceedings of the conference on Design, automation and test in Europe (2006), pp. 164-169. by Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Dennis Sylvester posted to combinational-logic modeling ser static by mrsmond on 2007-10-31 17:09:40 as
	Analysis of single-event effects in combinational logic-simulation of the AM2901 bitslice processor [My Copy] Nuclear Science, IEEE Transactions on In Nuclear Science, IEEE Transactions on, Vol. 47, No. 6. (2000), pp. 2609-2615. by L. W. Massengill, A. E. Baranski, D. O. Van Nort, J. Meng, B. L. Bhuva posted to combinational-logic fault-analysis fault-injection ser simulation trend by mrsmond on 2007-10-25 16:30:05 as
	On latching probability of particle induced transients in combinational networks [My Copy] Fault-Tolerant Computing, 1994. FTCS-24. Digest of Papers., Twenty-Fourth International Symposium on In Fault-Tolerant Computing, 1994. FTCS-24. Digest of Papers., Twenty-Fourth International Symposium on (1994), pp. 340-349. by P. Liden, P. Dahlgren, R. Johansson, J. Karlsson posted to combinational-logic modeling seu by mrsmond on 2007-10-25 16:27:21 as
	Modeling Soft Errors at Device and Logic Level for combinational circuits [My Copy] IEEE Transactions on Dependable and Secure Computing (September 2007) by Rajaraman Ramanarayanan, Vijay S. Degalahal, Ramakrishnan Krishnan, et al.Jungsub Kim, Vijaykrishnan Narayanan, Yuan Xie, Mary J. Irwin, Kenan Unlu posted to combinational-logic modeling ser by mrsmond on 2007-10-25 16:05:42 as
	Load and logic co-optimization for design of soft-error resistant nanometer CMOS circuits [My Copy] On-Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International (2005), pp. 35-40. by Y. S. Dhillon, A. U. Diril, A. Chatterjee, C. Metra posted to combinational-logic energy-analysis fault-analysis fault-tolerance toread transient-faults by mrsmond on 2007-07-05 14:35:54 as
	Combinational logic soft error analysis and protection [My Copy] On-Line Testing Symposium, 2006. IOLTS 2006. 12th IEEE International (2006), 6 pp.. by A. K. Nieuwland, S. Jasarevic, G. Jerin posted to combinational-logic fault-analysis fault-tolerance by mrsmond on 2007-07-05 10:35:52 as
	Prediction of transient induced by neutron/proton in CMOS combinational logic cells [My Copy] On-Line Testing Symposium, 2006. IOLTS 2006. 12th IEEE International (2006), 9 pp.. by G. Hubert, A. Bougerol, F. Miller, et al.N. Buard, L. Anghel, T. Carriere, F. Wrobel, R. Gaillard posted to combinational-logic fault-analysis neutron proton ser simulation transient-faults by mrsmond on 2007-07-04 14:04:42 as
	A model for transient fault propagation in combinatorial logic [My Copy] On-Line Testing Symposium, 2003. IOLTS 2003. 9th IEEE (2003), pp. 111-115. by M. Omana, G. Papasso, D. Rossi, C. Metra posted to combinational-logic fault-analysis modeling simulation by mrsmond on 2007-06-27 12:13:07 as
	Modeling the effect of technology trends on the soft error rate of combinational logic [My Copy] Dependable Systems and Networks, 2002. Proceedings. International Conference on (2002), pp. 389-398. by P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, L. Alvisi posted to combinational-logic importance--high ser shrinking trend by mrsmond on 2006-10-16 16:15:49 as

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jabref-file-import-09-05-08	272
fault-tolerance	31
ser	18
modeling	17
reliability	17
architecture	16
trend	15
toread	14
combinational-logic	12
soft-errors	12
computer	11
review	11
transient-faults	11
engd	10
have-paper-copy	10
memory	10
randd-reading-group	10
seu	10
fault-analysis	9
fault-injection	9
not-related-to-engd	9
semiconductor	9
simulation	9
system-level	9
theory	9
variability	9
circuit-level	8
energy-analysis	8
on-chip-communication	8
importance--high	7
interconnect	7
physics	7
cpu	6
error-correction	6
fault-detection	6
microarchitecture	6
pers-reading-group	6
circuit	5
computing-history	5
design	5
dynamic-voltage-scaling	5
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formal-methods	5
management	5
maths	5
network-on-chip	5
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business	3
computer-science	3
interesting-rating--1	3
interesting-rating--4	3
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proton	1
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redundancy	1
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testing	1
testtag	1

mrsmond's combinational-logic [12 articles] Export

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