Validation of hardware error recovery mechanisms for the SPARC64 V microprocessor Export

@proceedings{citeulike:4955373, abstract = {The SPARC64 V microprocessor is designed for use in high-reliability, large-scale unix servers. In addition to implementing ECC for large SRAM arrays, the SPARC64 V microprocessor incorporates error detection and recovery mechanisms for processor logic circuits and smaller SRAM arrays. The effectiveness of these error recovery mechanisms was validated via accelerated neutron testing of Fujitsupsilas commercial unix server, the PRIMEPOWER 650. Soft errors generated in SRAM arrays were completely recovered by the implemented hardware mechanisms, and only 6.4\% of the estimated neutron-induced logic circuit faults manifested as errors, 76\% of which were recovered by hardware. From these tests, the soft error failure rate of the SPARC64 V microprocessor due to atmospheric neutron hits was confirmed to be well below 10 FIT.}, author = {Ando, H. and Kan, R. and Tosaka, Y. and Takahisa, K. and Hatanaka, K.}, booktitle = {Dependable Systems and Networks With FTCS and DCC, 2008. DSN 2008. IEEE International Conference on}, citeulike-article-id = {4955373}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/DSN.2008.4630071}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4630071}, doi = {10.1109/DSN.2008.4630071}, journal = {Dependable Systems and Networks With FTCS and DCC, 2008. DSN 2008. IEEE International Conference on}, keywords = {fault-injection, hardware-fault, hardware-implemented-fault-tolerance, reliability, soft-error}, pages = {62--69}, posted-at = {2009-06-25 12:17:11}, priority = {0}, title = {Validation of hardware error recovery mechanisms for the SPARC64 V microprocessor}, url = {http://dx.doi.org/10.1109/DSN.2008.4630071}, year = {2008} }

TY - CONF ID - citeulike:4955373 L3 - citeulike-article-id:4955373 N2 - The SPARC64 V microprocessor is designed for use in high-reliability, large-scale unix servers. In addition to implementing ECC for large SRAM arrays, the SPARC64 V microprocessor incorporates error detection and recovery mechanisms for processor logic circuits and smaller SRAM arrays. The effectiveness of these error recovery mechanisms was validated via accelerated neutron testing of Fujitsupsilas commercial unix server, the PRIMEPOWER 650. Soft errors generated in SRAM arrays were completely recovered by the implemented hardware mechanisms, and only 6.4% of the estimated neutron-induced logic circuit faults manifested as errors, 76% of which were recovered by hardware. From these tests, the soft error failure rate of the SPARC64 V microprocessor due to atmospheric neutron hits was confirmed to be well below 10 FIT. JF - Dependable Systems and Networks With FTCS and DCC, 2008. DSN 2008. IEEE International Conference on EP - 69 TI - Validation of hardware error recovery mechanisms for the SPARC64 V microprocessor T2 - Dependable Systems and Networks With FTCS and DCC, 2008. DSN 2008. IEEE International Conference on SP - 62 KW - fault-injection KW - hardware-fault KW - hardware-implemented-fault-tolerance KW - reliability KW - soft-error AU - Ando, H AU - Kan, R AU - Tosaka, Y AU - Takahisa, K AU - Hatanaka, K PY - 2008/// UR - http://dx.doi.org/10.1109/DSN.2008.4630071 ER -