nathalie's library 140 articles Export

	The "quiet" state-a new approach to low-power multiplier design [My Copy] Signals, Systems and Computers, 2003. Conference Record of the Thirty-Seventh Asilomar Conference on, Vol. 2 (2003), pp. 2222-2226 Vol.2. by N. Mallios, N. Burgess posted to activity arithmetic for_thesis multiplier power by nathalie on 2006-10-02 05:07:12 as
	Wordlength as an Architectural Parameter for Reconfigurable Computing Devices [My Copy] In FPL '02: Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications (2002), pp. 667-676. by Tony Stansfield posted to architecture area arithmetic for_thesis fpga lut reconfigurable_computing routing by nathalie on 2006-09-05 06:44:28 as
	Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs [My Copy] In 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (2006) by C. H. Ho, P. H. W. Leong, W. Luk, S. J. E. Wilton, S. Lopez-Buedo posted to adder architecture arithmetic benchmarks dsp embedded floating_point for_thesis multiplier performance xilinx by nathalie on 2006-09-04 20:29:58 as
	Design Techniques to Reduce Power Consumption [My Copy] XCell Jornal (Quarter 3 2005) by Arthur Yang posted to for_thesis fpga power power_estimation xilinx by nathalie on 2006-09-02 01:01:20 as along with 1 person ceegrs2
	Power-aware Technology Mapping for LUT-based FPGAs [My Copy] Field-Programmable Technology, 2002. (FPT). Proceedings. 2002 IEEE International Conference on In Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology (2002), pp. 211-218. by J. H. Anderson, F. N. Najm posted to activity algorithms for_thesis fpl_paper fpt_paper logic_synthesis lut power power_estimation probability technology_mapping xilinx by nathalie on 2006-09-01 06:55:25 as along with 1 person ceegrs2
	Dynamic Voltage Scaling for Commercial FPGAs [My Copy] Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology (2005), pp. 173-180. by C. T. Chow, L. S. M. Tsui, P. H. W. Leong, W. Luk, S. J. E. Wilton posted to altera architecture for_thesis fpga fpl_paper fpt_paper power power_estimation vlsi xilinx by nathalie on 2006-09-01 06:46:27 as along with 2 people reactgary ceegrs2
	Power-aware RAM Mapping for FPGA Embedded Memory Blocks [My Copy] In FPGA'06: Proceedings of the International Symposium on Field Programmable Gate Arrays (2006), pp. 189-198. by Russell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy posted to activity algorithms altera for_thesis fpga logic_synthesis memory power by nathalie on 2006-09-01 05:55:51 as along with 1 person ceegrs2
	Measuring the Gap Between FPGAs and ASICs [My Copy] In FPGA'06: Proceedings of the Internation Symposium on Field Programmable Gate Arrays (2006), pp. 21-30. by Ian Kuon, Jonathan Rose posted to altera area asic benchmarks for_thesis fpga leakage performance power xilinx by nathalie on 2006-09-01 05:24:19 as along with 4 people ericschung hannibal_08 ceegrs2 JonsonXP
	A 90nm Low-power FPGA for Battery-powered Applications [My Copy] In FPGA'06: Proceedings of the internation symposium on Field programmable gate arrays (2006), pp. 3-11. by Tim Tuan, Sean Kao, Arif Rahman, Satyaki Das, Steve Trimberger posted to architecture for_thesis fpga leakage power xilinx by nathalie on 2006-09-01 05:17:34 as along with 1 person ceegrs2
	FPGA Power Reduction Using Configurable Dual-Vdd [My Copy] Design Automation Conference, 2004. Proceedings. 41st In Proceedings of the 41st Design Automation Conference (2004), pp. 735-740. by Fei Li, Yan Lin, Lei He posted to architecture for_thesis fpga leakage power spice vlsi by nathalie on 2006-09-01 04:59:15 as along with 1 person ceegrs2
	Active Leakage Power Optimization for FPGAs [My Copy] IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 3. (2006), pp. 423-437. by J. H. Anderson, F. N. Najm posted to algorithms for_thesis fpga leakage lut power xilinx by nathalie on 2006-09-01 02:18:26 as along with 1 person ceegrs2
	The Design of a Low Energy FPGA [My Copy] Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on In Proceedings. 1999 International Symposium on Low Power Electronics and Design (1999), pp. 188-193. by V. George, Hui Zhang, J. Rabaey posted to architecture for_thesis fpga interconnect lut power power_estimation power_measurement routing xilinx by nathalie on 2006-09-01 01:45:28 as
	Low-power High-level Synthesis for FPGA Architectures [My Copy] Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on In Proceedings of the 2003 International Symposium on Low Power Electronics and Design (2003), pp. 134-139. by Deming Chen, J. Cong, Yiping Fan posted to activity fpga interconnect power power_estimation synthesis by nathalie on 2006-09-01 01:34:03 as
	Power Estimation Techniques for FPGAs [My Copy] IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 10. (2004), pp. 1015-1027. by J. H. Anderson, F. N. Najm posted to activity for_thesis fpga interconnect power power_estimation vlsi xilinx by nathalie on 2006-09-01 01:12:59 as along with 1 person ceegrs2
	There is Life Left in ASICs [My Copy] In Proceedings of the 2003 International Symposium on Physical Design (2003), pp. 48-50. by Leon Stok, John Cohn posted to asic for_thesis fpga power vlsi by nathalie on 2006-09-01 01:05:13 as along with 1 person ceegrs2
	Practical Low Power Digital VLSI Design [My Copy] (01 August 1997) by Gary K. Yeap posted to activity for_thesis lag_one power power_estimation probability transition_density vlsi by nathalie on 2006-08-31 00:49:32 as
	Low Power CMOS Circuits: Technology, Logic Design and CAD Tools [My Copy] (2006) edited by Christian Piguet posted to arithmetic digital_logic for_thesis power power_estimation vlsi by nathalie on 2006-08-31 00:46:09 as
	Switching Activity Analysis Considering Spatioternporal Correlations [My Copy] Computer-Aided Design, 1994., IEEE/ACM International Conference on (1994), pp. 294-299. by R. Marculescu, D. Marculescu, M. Pedram posted to activity for_thesis lag_one power power_estimation probability transition_density by nathalie on 2006-08-31 00:26:37 as
	Interactive SPICE User Guide [My Copy] by T. Quarles, D. Pederson, R. Newton, A. Sangiovanni-Vincentelli, Christopher Wayne posted to for_thesis spice by nathalie on 2006-08-30 05:32:28 as
	A survey of power estimation techniques in VLSI circuits [My Copy] Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Vol. 2, No. 4. (1994), pp. 446-455. by F. N. Najm posted to vlsi for_thesis power power_estimation printed probability by nathalie on 2006-08-30 04:23:09 as along with 2 people mushunl ceegrs2
	Fundamentals of Digital Logic with Verilog Design [My Copy] (20 August 2002) by Stephen Brown, Zvonko Vranesic posted to altera digital_logic for_thesis fpga by nathalie on 2006-08-29 06:31:28 as
	Directional and single-driver wires in FPGA interconnect [My Copy] Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on (2004), pp. 41-48. by G. Lemieux, E. Lee, M. Tom, A. Yu posted to altera architecture for_thesis fpga interconnect routing xilinx by nathalie on 2006-08-28 04:10:16 as
	Field-Programmable Gate Array Architectures [My Copy] In Algorithms for VLSI Physical Design Automation (2006) by Steven J. E. Wilton, Nathalie, Scott Chin, Kara K. W. Poon edited by C. Alpert, D. Mehta, S. Sapatnekar posted to architecture coarse_grained_architectures for_thesis fpga interconnect lut memory by nathalie on 2006-08-28 01:32:46 as
	Berkeley Logic Interchange Format [My Copy] (6 September 1996) posted to for_thesis fpga placement power_estimation by nathalie on 2006-08-11 23:41:45 as
	HHVPR Manual [My Copy] (18 July 2005) by S. J. E. Wilton posted to architecture arithmetic dsp for_thesis memory multiplier power power_estimation printed by nathalie on 2006-08-11 23:28:30 as
	A New Switch Block for Segmented FPGAs [My Copy] In FPL '99: Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications (1999), pp. 274-281. by Imran M. Masud, Steven J. E. Wilton posted to architecture for_thesis fpga interconnect routing by nathalie on 2006-08-11 06:24:42 as
	Universal switch modules for FPGA design [My Copy] ACM Trans. Des. Autom. Electron. Syst., Vol. 1, No. 1. (January 1996), pp. 80-101. by Yao-Wen Chang, D. F. Wong, C. K. Wong posted to architecture for_thesis fpga interconnect routing by nathalie on 2006-08-11 06:21:38 as
	Architectures and Algorithms for Field-Programmable Gate Arrays with Embedded Memory [My Copy] (1997) by S. J. E. Wilton posted to algorithms architecture fpga memory by nathalie on 2006-08-11 06:18:29 as
	On two-step routing for FPGAS [My Copy] In ISPD '97: Proceedings of the 1997 international symposium on Physical design (1997), pp. 60-66. by Guy G. F. Lemieux, Stephen D. Brown, Daniel Vranesic posted to architecture for_thesis interconnect routing xilinx by nathalie on 2006-08-11 06:12:00 as
	A new generation of digital VLSI CAD tools based on probability [My Copy] System Theory, 1995., Proceedings of the Twenty-Seventh Southeastern Symposium on (1995), pp. 348-352. by N. Abdallah, J. Dunoyer, P. B. Sabet posted to actel for_thesis printed probability transition_density vlsi by nathalie on 2006-08-11 00:27:04 as
	Transition density: a new measure of activity in digital circuits [My Copy] Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 12, No. 2. (1993), pp. 310-323. by F. N. Najm posted to activity for_thesis fpl_paper fpt_paper power_estimation printed transition_density vlsi by nathalie on 2006-07-06 19:31:29 as
	The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays [My Copy] In International Conference on Field-Programmable Logic and its Applications (August 2004), pp. 719-728. by S. J. E. Wilton, S. S. Ang, W. Luk posted to for_thesis fpga fpl_paper pipelined power by nathalie on 2006-06-26 23:10:49 as along with 1 person ceegrs2
	Activity Estimation For Field-Programmable Gate Arrays [My Copy] In International Conference on Field-Programmable Logic and Applications (August 2006) by J. Lamoureux, S. J. E. Wilton posted to activity for_thesis fpl_paper fpt_paper power_estimation by nathalie on 2006-06-23 18:26:30 as
	SIS: A system for sequential circuit synthesis [My Copy] (1992) by E. M. Sentovich, K. J. Singh, L. Lavagno, et al.C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, Sangiovanni A. Vincentelli posted to for_thesis fpl_paper fpt_paper logic_synthesis synthesis vlsi by nathalie on 2006-06-20 23:21:57 as
	The RAW benchmark suite: computation structures for general purpose computing [My Copy] FPGAs for Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium on (1997), pp. 134-143. by J. Babb, M. Frank, V. Lee, et al.E. Waingold, R. Barua, M. Taylor, J. Kim, S. Devabhaktuni, A. Agarwal posted to architecture benchmarks for_thesis fpga fpt_paper integer matrix reconfigurable_computing by nathalie on 2006-05-16 23:44:16 as
	Wormhole run-time reconfiguration [My Copy] In FPGA '97: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays (1997), pp. 79-85. by Ray Bittner, Peter Athanas posted to architecture floating_point fpga multiplier printed reconfigurable_computing runtime_reconfig by nathalie on 2006-04-30 23:42:42 as
	Power modeling and characteristics of field programmable gate arrays [My Copy] Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 24, No. 11. (2005), pp. 1712-1724. by Fei Li, Y. Lin, Lei He, Deming Chen, J. Cong posted to for_thesis fpga power power_estimation printed by nathalie on 2006-04-27 19:43:42 as along with 1 person ceegrs2
	PowerPlay Power Analyzer [My Copy] In Quartus II Handbook, Vol. 3 (October 2005) by Altera posted to altera for_thesis fpga power power_estimation by nathalie on 2006-04-27 18:59:47 as
	Xilinx Development System Reference Guide 8.1i [My Copy] (09 December 2005) by Xilinx posted to for_thesis fpga power_estimation xilinx by nathalie on 2006-04-27 18:37:44 as
	PowerPlay Early Power Estimator User Guide for Stratix, Stratix GX, and Cyclone FPGAs [My Copy] (October 2005) by Altera posted to altera for_thesis fpga power power_estimation by nathalie on 2006-04-27 17:29:48 as
	PowerPlay Early Power Estimator User Guide for Stratix II, Stratix II GX and Hardcopy II [My Copy] (December 2005) by Altera posted to altera for_thesis fpga power power_estimation by nathalie on 2006-04-27 17:19:10 as
	Xilinx Web Power Tools [My Copy] (27 April 2006) by Xilinx posted to for_thesis fpga power power_estimation xilinx by nathalie on 2006-04-27 16:57:28 as
	Virtex-4 XPower - Early Power Estimator v8.1 [My Copy] (27 April 2006) by Xilinx posted to for_thesis fpga power_estimation xilinx by nathalie on 2006-04-27 16:11:12 as
	Stratix II Device Handbook [My Copy] (2005) by Altera posted to altera for_thesis fpga by nathalie on 2006-04-27 15:34:49 as
	UG070: Virtex-4 User Guide [My Copy] (March 2006) by Xilinx posted to for_thesis fpga xilinx by nathalie on 2006-04-27 04:01:42 as
	Architecture of field-programmable gate arrays [My Copy] Proceedings of the IEEE, Vol. 81, No. 7. (1993), pp. 1013-1029. by J. Rose, El, A. Sangiovanni-Vincentelli posted to architecture for_thesis fpga by nathalie on 2006-04-25 23:33:19 as
	Power Estimation for Field Programmable Gate Arrays [My Copy] (August 2002) by Kara K. Poon posted to for_thesis fpga power power_estimation by nathalie on 2006-04-25 22:00:08 as
	Architecture and CAD for Deep-Submicron FPGAs (The International Series in Engineering and Computer Science) [My Copy] (31 March 1999) by Vaughn Betz, Jonathan Rose, Alexander Marquardt posted to architecture for_thesis fpga placement routing by nathalie on 2006-04-25 18:34:18 as along with 1 person JonsonXP
	Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation [My Copy] In GLS '99: Proceedings of the Ninth Great Lakes Symposium on VLSI (1999) by Janardhan H. Satyanarayana, Keshab K. Parhi posted to arithmetic dsp for_thesis multiplier power power_estimation by nathalie on 2006-04-18 16:58:07 as
	Information theoretic measures for power analysis [logic design] [My Copy] Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 15, No. 6. (1996), pp. 599-610. by D. Marculescu, R. Marculescu, M. Pedram posted to for_thesis fpl_paper power power_estimation printed by nathalie on 2006-03-11 07:01:07 as

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fpga	83
for_thesis	61
power	48
arithmetic	38
power_estimation	37
printed	33
xilinx	32
architecture	30
annotation	21
fpl_paper	21
multiplier	20
eece519	20
altera	16
routing	15
eece519proj	15
interconnect	14
vlsi	13
adder	10
clustering	10
dsp	10
floating_point	9
activity	9
synthesis	7
cpsc521	7
fpt_paper	6
placement	6
packing	6
lut	6
coarse_grained_architectures	5
probability	5
logic_synthesis	5
leakage	4
algorithms	4
area	4
reconfigurable_computing	4
transition_density	4
memory	4
technology_mapping	3
matrix	3
power_measurement	3
digital_library	3
embedded	3
benchmarks	3
division	3
performance	3
integer	2
spice	2
asic	2
pipelined	2
discrete_optimization_problems	2
semantic_web	2
digital_logic	2
sequential_ordering_problem	2
lag_one	2
actel	2
deep_submicron	1
image_processing	1
hamiltonian	1
knowledge_management	1
information_extraction	1
parametrized	1
synopsys	1
parallel	1
sign_detection	1
square_root	1
cost	1
runtime_reconfig	1
minimum	1
instruction_set	1
subtractor	1
processors	1
fixed_point	1
path	1

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