VLSI Design, 1994., Proceedings of the Seventh International Conference on (1994), pp. 265-270.
Abstract
Power has become an important optimizing parameter due to increasing use of portable and remote electronic systems. In a CMOS circuit, node activity is directly proportional to the amount of power drawn. We analyze activity metrics at high level for adders and multipliers and derive architectural transformations for synthesizing low power circuits. The goal is to identify data flow graph transformations that reduce overall circuit activity rather than accurate prediction of power consumption. It is shown experimentally that the transformations are ...
Note (first note only)
Might also be useful for thesis
They base this on Stochastic processes. The procedure is based on the stochastic activity process being strict-sense stationary.
Avg activity at output of a 2-input adder is approx max of avg activity of its inputs.
For constant multipliers, avg activity of output decreases w/ abs val of constant.
Can use these properties to transform linear ccts using associativity and commutativity to minimize expected activity. However, these transformations may increase delay.
=> Properties force additions w/ high activity to
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