Compilation and Pipeline Synthesis for Reconfigurable Architectures - High Performance by Configware Export

@misc{citeulike:572490, abstract = {. This paper gives a survey of a novel programming method for reconfigurable architectures. It combines techniques from vectorizing compilers, high-level synthesis, and hardware/software codesign: An imperative high-level language program specifies both the host program (software) and the coprocessor configuration (hardware) of the application. This renders reconfigurable architectures useful for users without hardware design experience. First, the input program is analyzed and vectorized....}, author = {Weinhardt, M.}, citeulike-article-id = {572490}, citeulike-linkout-0 = {http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.25.2861}, keywords = {hardware-compilation, reconfigurable-computing}, posted-at = {2006-04-01 21:29:02}, priority = {2}, title = {Compilation and Pipeline Synthesis for Reconfigurable Architectures - High Performance by Configware}, url = {http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.25.2861}, year = {1997} }

TY - GEN ID - citeulike:572490 L3 - citeulike-article-id:572490 N2 - . This paper gives a survey of a novel programming method for reconfigurable architectures. It combines techniques from vectorizing compilers, high-level synthesis, and hardware/software codesign: An imperative high-level language program specifies both the host program (software) and the coprocessor configuration (hardware) of the application. This renders reconfigurable architectures useful for users without hardware design experience. First, the input program is analyzed and vectorized.... TI - Compilation and Pipeline Synthesis for Reconfigurable Architectures - High Performance by Configware KW - hardware-compilation KW - reconfigurable-computing AU - Weinhardt, M PY - 1997/// UR - http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.25.2861 ER -