How Programmable is Reconfigurable Hardware?: A Design Model for Reconfigurable Architectures Export

@misc{citeulike:574714, abstract = {This paper address the need for additional application development support by proposing a system-level asynchronous model, based on CSP (Communicating Sequential Processes) [2], and implementing an FPGA runtime environment allowing user-level `task' objects to communicate via Handel-C channels}, author = {Self, R. P. and Fleury, M. and Downton, A. C.}, citeulike-article-id = {574714}, citeulike-linkout-0 = {http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.1.8922}, keywords = {hardware-compilation, reconfigurable-computing}, posted-at = {2006-04-03 16:39:03}, priority = {2}, title = {How Programmable is Reconfigurable Hardware?: A Design Model for Reconfigurable Architectures}, url = {http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.1.8922} }

TY - GEN ID - citeulike:574714 L3 - citeulike-article-id:574714 N2 - This paper address the need for additional application development support by proposing a system-level asynchronous model, based on CSP (Communicating Sequential Processes) [2], and implementing an FPGA runtime environment allowing user-level `task' objects to communicate via Handel-C channels TI - How Programmable is Reconfigurable Hardware?: A Design Model for Reconfigurable Architectures KW - hardware-compilation KW - reconfigurable-computing AU - Self, RP AU - Fleury, M AU - Downton, AC UR - http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.1.8922 ER -