Reactive NUCA: near-optimal block placement and replication in distributed caches Export

@inproceedings{Hardavellas09, abstract = {Increases in on-chip communication delay and the large working sets of server and scientific workloads complicate the design of the on-chip last-level cache for multicore processors. The large working sets favor a shared cache design that maximizes the aggregate cache capacity and minimizes off-chip memory requests. At the same time, the growing on-chip communication delay favors core-private caches that replicate data to minimize delays on global wires. Recent hybrid proposals offer lower average latency than conventional designs, but they address the placement requirements of only a subset of the data accessed by the application, require complex lookup and coherence mechanisms that increase latency, or fail to scale to high core counts.}, address = {New York, NY, USA}, author = {Hardavellas, Nikos and Ferdman, Michael and Falsafi, Babak and Ailamaki, Anastasia}, booktitle = {ISCA '09: Proceedings of the 36th annual international symposium on Computer architecture}, citeulike-article-id = {5925241}, citeulike-linkout-0 = {http://portal.acm.org/citation.cfm?id=1555779}, citeulike-linkout-1 = {http://dx.doi.org/10.1145/1555754.1555779}, doi = {10.1145/1555754.1555779}, isbn = {978-1-60558-526-0}, keywords = {data, placement}, location = {Austin, TX, USA}, pages = {184--195}, posted-at = {2009-10-12 09:47:06}, priority = {2}, publisher = {ACM}, title = {Reactive NUCA: near-optimal block placement and replication in distributed caches}, url = {http://dx.doi.org/10.1145/1555754.1555779}, year = {2009} }

TY - CONF ID - Hardavellas09 L3 - citeulike-article-id:5925241 N2 - Increases in on-chip communication delay and the large working sets of server and scientific workloads complicate the design of the on-chip last-level cache for multicore processors. The large working sets favor a shared cache design that maximizes the aggregate cache capacity and minimizes off-chip memory requests. At the same time, the growing on-chip communication delay favors core-private caches that replicate data to minimize delays on global wires. Recent hybrid proposals offer lower average latency than conventional designs, but they address the placement requirements of only a subset of the data accessed by the application, require complex lookup and coherence mechanisms that increase latency, or fail to scale to high core counts. CY - Austin, TX, USA SN - 978-1-60558-526-0 AD - New York, NY, USA EP - 195 TI - Reactive NUCA: near-optimal block placement and replication in distributed caches PB - ACM T2 - ISCA '09: Proceedings of the 36th annual international symposium on Computer architecture SP - 184 KW - data KW - placement AU - Hardavellas, Nikos AU - Ferdman, Michael AU - Falsafi, Babak AU - Ailamaki, Anastasia PY - 2009/// UR - http://dx.doi.org/10.1145/1555754.1555779 ER -