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In Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on, Vol. 3 (2002), pp. III-281-III-284 vol.3, doi:10.1109/iscas.2002.1010215 Key: citeulike:11238472
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This paper proposes a high-speed FFT processor for orthogonal frequency-division multiplexing (OFDM) systems. The proposed architecture uses a single-memory for a small hardware size and uses a radix-4 algorithm for high speed. Its memory is partitioned into four banks for high-speed computation. It uses an in-place memory strategy that stores butterfly outputs in the same memory location used by butterfly inputs. The architecture has been modeled by VHDL and logic synthesis has been performed using the Samsung
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