A 180-mV subthreshold FFT processor using a minimum energy design methodology Export

@article{citeulike:3480757, abstract = {In emerging embedded applications such as wireless sensor networks, the key metric is minimizing energy dissipation rather than processor speed. Minimum energy analysis of CMOS circuits estimates the optimal operating point of clock frequencies, supply voltage, and threshold voltage according to A. Chandrakasan et al. (see ibid., vol.27, no.4, p.473-84, Apr. 1992). The minimum energy analysis shows that the optimal power supply typically occurs in subthreshold (e.g., supply voltages that are below device thresholds). New subthreshold logic and memory design methodologies are developed and demonstrated on a fast Fourier transform (FFT) processor. The FFT processor uses an energy-aware architecture that allows for variable FFT length (128-1024 point), variable bit-precision (8 b and 16 b) and is designed to investigate the estimated minimum energy point. The FFT processor is fabricated using a standard 0.18-μm CMOS logic process and operates down to 180 mV. The minimum energy point for the 16-b 1024-point FFT processor occurs at 350-mV supply voltage where it dissipates 155 nJ/FFT at a clock frequency of 10 kHz.}, author = {Wang, A. and Chandrakasan, A.}, booktitle = {Solid-State Circuits, IEEE J. of}, citeulike-article-id = {3480757}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/JSSC.2004.837945}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1375015}, comment = {0.18um CMOS; 2.6 mm x 2.1 mm; 180 mV IS Impl. Details: 128-1024 point FFT, 16 bit 1024 point energy is 155nJ/FFT with a clock of 10kHz This is a cusotm digital processor for computing the FFT. It has a variable data width of 8 - 16 b and a variable number of points. The primary concern is the lowest energy point, which is shown to be in the subthreshold region.}, doi = {10.1109/JSSC.2004.837945}, journal = {Solid-State Circuits, IEEE Journal of}, keywords = {fft, impedance, low\_power}, number = {1}, pages = {310--319}, posted-at = {2008-11-04 19:46:11}, priority = {0}, title = {A 180-mV subthreshold FFT processor using a minimum energy design methodology}, url = {http://dx.doi.org/10.1109/JSSC.2004.837945}, volume = {40}, year = {2005} }

TY - JOUR ID - citeulike:3480757 L3 - citeulike-article-id:3480757 N2 - In emerging embedded applications such as wireless sensor networks, the key metric is minimizing energy dissipation rather than processor speed. Minimum energy analysis of CMOS circuits estimates the optimal operating point of clock frequencies, supply voltage, and threshold voltage according to A. Chandrakasan et al. (see ibid., vol.27, no.4, p.473-84, Apr. 1992). The minimum energy analysis shows that the optimal power supply typically occurs in subthreshold (e.g., supply voltages that are below device thresholds). New subthreshold logic and memory design methodologies are developed and demonstrated on a fast Fourier transform (FFT) processor. The FFT processor uses an energy-aware architecture that allows for variable FFT length (128-1024 point), variable bit-precision (8 b and 16 b) and is designed to investigate the estimated minimum energy point. The FFT processor is fabricated using a standard 0.18-μm CMOS logic process and operates down to 180 mV. The minimum energy point for the 16-b 1024-point FFT processor occurs at 350-mV supply voltage where it dissipates 155 nJ/FFT at a clock frequency of 10 kHz. IS - 1 JF - Solid-State Circuits, IEEE Journal of EP - 319 TI - A 180-mV subthreshold FFT processor using a minimum energy design methodology VL - 40 T2 - Solid-State Circuits, IEEE J. of SP - 310 KW - fft KW - impedance KW - low_power N1 - 0.18um CMOS; 2.6 mm x 2.1 mm; 180 mV IS Impl. Details: 128-1024 point FFT, 16 bit 1024 point energy is 155nJ/FFT with a clock of 10kHz This is a cusotm digital processor for computing the FFT. It has a variable data width of 8 - 16 b and a variable number of points. The primary concern is the lowest energy point, which is shown to be in the subthreshold region. AU - Wang, A AU - Chandrakasan, A PY - 2005/// UR - http://dx.doi.org/10.1109/JSSC.2004.837945 ER -