A 6b 0.2-to-0.9V Highly Digital Flash ADC with Comparator Redundancy Export

@proceedings{citeulike:3480912, abstract = {Microsensor wireless networks and implanted biomedical devices have emerged as exciting new application domains. These applications are highly energy constrained and require flexible, integrated, energy-efficient ADC modules that can ideally operate at the same supply voltage as digital circuits. In many applications, the performance requirements are quite modest (100s kS/s). This paper presents a highly digital ADC architecture compatible with advanced CMOS processes, capable of operating down to a supply voltage of 200mV (i.e., subthreshold regime) and up to 900mV. However, leakage and device variation must be addressed, particularly at low supply voltages.}, author = {Daly, D. C. and Chandrakasan, A. P.}, booktitle = {Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International}, citeulike-article-id = {3480912}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/ISSCC.2008.4523303}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4523303}, comment = {Subthreshold ADC. Very low power. Addresses large mismatch due to fabrication error and leakage current due to sub-th operation. Note that with a total power consumption of 2.84uW, it may not be that much lower power than a resistive ADC (2V^2/1MOhm = 4uW) ---=note-separator=--- Clever Circuits: Multiple techniques for limiting leakage from a sample and hold cap. 1) Clock voltage boost ckt 2) Buffer feedback in sample switch. Buffer is simple self biased source follower.}, doi = {10.1109/ISSCC.2008.4523303}, journal = {Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International}, keywords = {adc, clever, low\_power, subthreshold}, pages = {554--635}, posted-at = {2008-11-04 21:34:08}, priority = {0}, title = {A 6b 0.2-to-0.9V Highly Digital Flash ADC with Comparator Redundancy}, url = {http://dx.doi.org/10.1109/ISSCC.2008.4523303}, year = {2008} }

TY - CONF ID - citeulike:3480912 L3 - citeulike-article-id:3480912 N2 - Microsensor wireless networks and implanted biomedical devices have emerged as exciting new application domains. These applications are highly energy constrained and require flexible, integrated, energy-efficient ADC modules that can ideally operate at the same supply voltage as digital circuits. In many applications, the performance requirements are quite modest (100s kS/s). This paper presents a highly digital ADC architecture compatible with advanced CMOS processes, capable of operating down to a supply voltage of 200mV (i.e., subthreshold regime) and up to 900mV. However, leakage and device variation must be addressed, particularly at low supply voltages. JF - Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International EP - 635 TI - A 6b 0.2-to-0.9V Highly Digital Flash ADC with Comparator Redundancy T2 - Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International SP - 554 KW - adc KW - clever KW - low_power KW - subthreshold N1 - Subthreshold ADC. Very low power. Addresses large mismatch due to fabrication error and leakage current due to sub-th operation. Note that with a total power consumption of 2.84uW, it may not be that much lower power than a resistive ADC (2V^2/1MOhm = 4uW) N1 - Clever Circuits: Multiple techniques for limiting leakage from a sample and hold cap. 1) Clock voltage boost ckt 2) Buffer feedback in sample switch. Buffer is simple self biased source follower. AU - Daly, DC AU - Chandrakasan, AP PY - 2008/// UR - http://dx.doi.org/10.1109/ISSCC.2008.4523303 ER -