Reducing MOSFET 1/f noise and power consumption by switched biasing Export

@article{citeulike:3851445, abstract = {Switched biasing is proposed as a technique for reducing the 1/f noise in MOSFET's. Conventional techniques, such as chopping or correlated double sampling, reduce the effect of 1/f noise in electronic circuits, whereas the switched biasing technique reduces the 1/f noise itself. Whereas noise reduction techniques generally lead to more power consumption, switched biasing can reduce the power consumption. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its intrinsic 1/f noise. As the 1/f noise is reduced at its physical roots, high frequency circuits, in which 1/f noise is being upconverted, can also benefit. This is demonstrated by applying switched biasing in a 0.8 \μm CMOS sawtooth oscillator. By periodically switching off the bias currents, during time intervals that they are not contributing to the circuit operation, a reduction of the 1/f noise induced phase noise by more than 8 dB is achieved, while the power consumption is also reduced by 30\%}, author = {Klumperink, E. A. M. and Gierkink, S. L. J. and van der Wel, A. P. and Nauta, B.}, booktitle = {Solid-State Circuits, IEEE Journal of}, citeulike-article-id = {3851445}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/4.848208}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=848208}, comment = {Interesting method to reduce 1/f noise by factor of 2 or 2.5. Basically they shut off the bias current for a short while.}, doi = {10.1109/4.848208}, journal = {Solid-State Circuits, IEEE Journal of}, keywords = {chopper, clever}, number = {7}, pages = {994--1001}, posted-at = {2009-01-05 22:18:44}, priority = {0}, title = {Reducing MOSFET 1/f noise and power consumption by switched biasing}, url = {http://dx.doi.org/10.1109/4.848208}, volume = {35}, year = {2000} }

TY - JOUR ID - citeulike:3851445 L3 - citeulike-article-id:3851445 N2 - Switched biasing is proposed as a technique for reducing the 1/f noise in MOSFET's. Conventional techniques, such as chopping or correlated double sampling, reduce the effect of 1/f noise in electronic circuits, whereas the switched biasing technique reduces the 1/f noise itself. Whereas noise reduction techniques generally lead to more power consumption, switched biasing can reduce the power consumption. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its intrinsic 1/f noise. As the 1/f noise is reduced at its physical roots, high frequency circuits, in which 1/f noise is being upconverted, can also benefit. This is demonstrated by applying switched biasing in a 0.8 μm CMOS sawtooth oscillator. By periodically switching off the bias currents, during time intervals that they are not contributing to the circuit operation, a reduction of the 1/f noise induced phase noise by more than 8 dB is achieved, while the power consumption is also reduced by 30% IS - 7 JF - Solid-State Circuits, IEEE Journal of EP - 1001 TI - Reducing MOSFET 1/f noise and power consumption by switched biasing VL - 35 T2 - Solid-State Circuits, IEEE Journal of SP - 994 KW - chopper KW - clever N1 - Interesting method to reduce 1/f noise by factor of 2 or 2.5. Basically they shut off the bias current for a short while. AU - Klumperink, EAM AU - Gierkink, SLJ AU - van der Wel, AP AU - Nauta, B PY - 2000/// UR - http://dx.doi.org/10.1109/4.848208 ER -