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A calibration-free 3V 16b 500kS/s 6mW 0.5mm² ADC with 0.13 μm CMOSVLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on In VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on (2004), pp. 76-77.
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Notes for this articleThis could be used to sample 25 sensors at a rate of 20kHz in an FFT array system. 100 sensors would take 2mm^2
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AbstractA calibration-free 3V 6mW 16-bit 500kS/s cyclic ADC with an active die area of 0.5mm<sup>2</sup> is implemented in a 0.13 μm CMOS. The proposed converter adopts a 2.5-bit/stage cyclic architecture and capacitor layout scheme to achieve improved matching accuracy, the DNL and INL of ±0.90 LSB and ±6.1 LSB, respectively.
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