A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC Export

@article{citeulike:3858586, abstract = {A 0.9 V third-order double-sampled delta-sigma audio ADC is presented. A new method using a combination of a switched-RC technique and a floating switched-capacitor double-sampling configuration enabled low-voltage operation without clock boosting or bootstrapping. A three-level quantizer with simple dynamic element matching was used to improve linearity. The prototype IC implemented in a 0.13 CMOS process achieves 92 dB DR, 91 dB SNR and 89 dB SNDR in a 24 kHz audio signal bandwidth, while consuming 1.5 mW from a 0.9 V supply. The prototype operates from 0.65 V to 1.5 V supply with minimal performance degradation.}, author = {Kim, Min G. and Ahn, Gil-Cho and Hanumolu, P. K. and Lee, Sang-Hyeon and Kim, Sang-Ho and You, Seung-Bin and Kim, Jae-Whui and Temes, G. C. and Moon, Un-Ku}, booktitle = {Solid-State Circuits, IEEE Journal of}, citeulike-article-id = {3858586}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/JSSC.2008.920329}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4494661}, comment = {Sigma Delta with sampling rate doubled. Some nice SC circuits and discussion of sigma Deltas}, doi = {10.1109/JSSC.2008.920329}, journal = {Solid-State Circuits, IEEE Journal of}, keywords = {adc, clever}, number = {5}, pages = {1195--1206}, posted-at = {2009-01-07 19:48:18}, priority = {0}, title = {A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC}, url = {http://dx.doi.org/10.1109/JSSC.2008.920329}, volume = {43}, year = {2008} }

TY - JOUR ID - citeulike:3858586 L3 - citeulike-article-id:3858586 N2 - A 0.9 V third-order double-sampled delta-sigma audio ADC is presented. A new method using a combination of a switched-RC technique and a floating switched-capacitor double-sampling configuration enabled low-voltage operation without clock boosting or bootstrapping. A three-level quantizer with simple dynamic element matching was used to improve linearity. The prototype IC implemented in a 0.13 CMOS process achieves 92 dB DR, 91 dB SNR and 89 dB SNDR in a 24 kHz audio signal bandwidth, while consuming 1.5 mW from a 0.9 V supply. The prototype operates from 0.65 V to 1.5 V supply with minimal performance degradation. IS - 5 JF - Solid-State Circuits, IEEE Journal of EP - 1206 TI - A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC VL - 43 T2 - Solid-State Circuits, IEEE Journal of SP - 1195 KW - adc KW - clever N1 - Sigma Delta with sampling rate doubled. Some nice SC circuits and discussion of sigma Deltas AU - Kim, Min AU - Ahn, Gil-Cho AU - Hanumolu, PK AU - Lee, Sang-Hyeon AU - Kim, Sang-Ho AU - You, Seung-Bin AU - Kim, Jae-Whui AU - Temes, GC AU - Moon, Un-Ku PY - 2008/// UR - http://dx.doi.org/10.1109/JSSC.2008.920329 ER -