Strategies for Managing the Register File in RISC Export

@article{citeulike:2901913, abstract = {The RISC (reduced instruction set computer) architecture attempts to achieve high performance without resorting to complex instructions and irregular pipelining schemes. One of the novel features of this architecture is a large register file which is used to minimize the overhead involved in procedure calls and returns. This paper investigates several strategies for managing this register file. The costs of practical strategies are compared with a lower bound on this management overhead, obtained from a theoretical optimal strategy, for several register file sizes.}, author = {Tamir, Y. and Sequin, C. H.}, booktitle = {Computers, IEEE Transactions on}, citeulike-article-id = {2901913}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/TC.1983.1676149}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1676149}, doi = {10.1109/TC.1983.1676149}, journal = {Computers, IEEE Transactions on}, keywords = {architecture, computer, risc}, number = {11}, pages = {977--989}, posted-at = {2008-06-17 11:15:00}, priority = {2}, title = {Strategies for Managing the Register File in RISC}, url = {http://dx.doi.org/10.1109/TC.1983.1676149}, volume = {C-32}, year = {1983} }

TY - JOUR ID - citeulike:2901913 L3 - citeulike-article-id:2901913 N2 - The RISC (reduced instruction set computer) architecture attempts to achieve high performance without resorting to complex instructions and irregular pipelining schemes. One of the novel features of this architecture is a large register file which is used to minimize the overhead involved in procedure calls and returns. This paper investigates several strategies for managing this register file. The costs of practical strategies are compared with a lower bound on this management overhead, obtained from a theoretical optimal strategy, for several register file sizes. IS - 11 JF - Computers, IEEE Transactions on EP - 989 TI - Strategies for Managing the Register File in RISC VL - C-32 T2 - Computers, IEEE Transactions on SP - 977 KW - architecture KW - computer KW - risc AU - Tamir, Y AU - Sequin, CH PY - 1983/// UR - http://dx.doi.org/10.1109/TC.1983.1676149 ER -