IBM RISC System/6000: architecture and performance Export

@article{citeulike:2901936, abstract = {The IBM RISC System/6000, a superscalar microprocessor, is presented. The architecture of this processor has its instruction set specifically designed for a superscalar machine containing three independent units-branch, fixed-point, and floating-point. The design also emphasizes high-performance floating-point operations. The design principles are to offer maximum overlap of the three functional units, avoid dead cycles, and define instructions that can (for the most part) be completed at a rate of one per cycle. The branch cycle, fixed- and floating-point units, cache management, and performance are described. Benchmark results are given}, author = {Oehler, R. R. and Blasgen, M. W.}, booktitle = {Micro, IEEE}, citeulike-article-id = {2901936}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/40.87565}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=87565}, doi = {10.1109/40.87565}, journal = {Micro, IEEE}, keywords = {architecture, computer, risc}, number = {3}, pages = {14--17, 56-62}, posted-at = {2008-06-17 11:23:36}, priority = {2}, title = {IBM RISC System/6000: architecture and performance}, url = {http://dx.doi.org/10.1109/40.87565}, volume = {11}, year = {1991} }

TY - JOUR ID - citeulike:2901936 L3 - citeulike-article-id:2901936 N2 - The IBM RISC System/6000, a superscalar microprocessor, is presented. The architecture of this processor has its instruction set specifically designed for a superscalar machine containing three independent units-branch, fixed-point, and floating-point. The design also emphasizes high-performance floating-point operations. The design principles are to offer maximum overlap of the three functional units, avoid dead cycles, and define instructions that can (for the most part) be completed at a rate of one per cycle. The branch cycle, fixed- and floating-point units, cache management, and performance are described. Benchmark results are given IS - 3 JF - Micro, IEEE EP - 17, 56-62 TI - IBM RISC System/6000: architecture and performance VL - 11 T2 - Micro, IEEE SP - 14 KW - architecture KW - computer KW - risc AU - Oehler, RR AU - Blasgen, MW PY - 1991/// UR - http://dx.doi.org/10.1109/40.87565 ER -