Ray Tracing on the Cell Processor Export

@inproceedings{cellbe-raytracing, abstract = {Over the last three decades, higher CPU performance has been achieved almost exclusively by raising the CPU's clock rate. Today, the resulting power consumption and heat dissipation threaten to end this trend, and CPU designers are looking for alternative ways of providing more compute power. In particular, they are looking towards three concepts: a streaming compute model, vector-like SIMD units, and multi-core architectures. One particular example of such an architecture is the cell broadband engine architecture (CBEA), a multi-core processor that offers a raw compute power of up to 200 GFlops per 3.2 GHz chip. The cell bears a huge potential for compute-intensive applications like ray tracing, but also requires addressing the challenges caused by this processor's unconventional architecture. In this paper, we describe an implementation of realtime ray tracing on a cell. Using a combination of low-level optimized kernel routines, a streaming software architecture, explicit caching, and a virtual software-hyperthreading approach to hide DMA latencies, we achieve for a single cell a pure ray tracing performance of nearly one order of magnitude over that achieved by a commodity CPU}, author = {Benthin, C. and Wald, I. and Scherbaum, M. and Friedrich, H.}, citeulike-article-id = {1243198}, citeulike-linkout-0 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4061541}, journal = {Interactive Ray Tracing 2006, IEEE Symposium on}, keywords = {algorithm, cellbe, ray-tracing}, pages = {15--23}, posted-at = {2007-04-22 06:25:41}, priority = {0}, title = {Ray Tracing on the Cell Processor}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4061541}, year = {2006} }

TY - CONF ID - cellbe-raytracing L3 - citeulike-article-id:1243198 N2 - Over the last three decades, higher CPU performance has been achieved almost exclusively by raising the CPU's clock rate. Today, the resulting power consumption and heat dissipation threaten to end this trend, and CPU designers are looking for alternative ways of providing more compute power. In particular, they are looking towards three concepts: a streaming compute model, vector-like SIMD units, and multi-core architectures. One particular example of such an architecture is the cell broadband engine architecture (CBEA), a multi-core processor that offers a raw compute power of up to 200 GFlops per 3.2 GHz chip. The cell bears a huge potential for compute-intensive applications like ray tracing, but also requires addressing the challenges caused by this processor's unconventional architecture. In this paper, we describe an implementation of realtime ray tracing on a cell. Using a combination of low-level optimized kernel routines, a streaming software architecture, explicit caching, and a virtual software-hyperthreading approach to hide DMA latencies, we achieve for a single cell a pure ray tracing performance of nearly one order of magnitude over that achieved by a commodity CPU JF - Interactive Ray Tracing 2006, IEEE Symposium on EP - 23 TI - Ray Tracing on the Cell Processor SP - 15 KW - algorithm KW - cellbe KW - ray-tracing AU - Benthin, C AU - Wald, I AU - Scherbaum, M AU - Friedrich, H PY - 2006/// UR - http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4061541 ER -