sugaya's library 127 articles Export

	Low-density parity-check code constructions for hardware implementation [My Copy] Communications, 2004 IEEE International Conference on In Communications, 2004 IEEE International Conference on, Vol. 5 (2004), pp. 2573-2577 Vol.5. by E. Liao, Engling Yeo, B. Nikolic posted to architecture ldpc vlsi by sugaya on 2007-08-07 10:09:07 as
	New arithmetic coder/decoder architectures based on pipelining [My Copy] In ASAP '97: Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (1997) by R. R. Osorio, J. D. Bruguera posted to architecture vlsi by sugaya on 2007-08-07 10:00:26 as
	Multiple-symbol parallel decoding for variable length codes [My Copy] IEEE Trans. Very Large Scale Integr. Syst., Vol. 12, No. 7. (July 2004), pp. 676-685. by Jari Nikara, Stamatis Vassiliadis, Jarmo Takala, Petri Liuha posted to architecture vlsi by sugaya on 2007-08-07 09:56:05 as
	A new 2-D systolic digital filter architecture without global broadcast [My Copy] IEEE Trans. Very Large Scale Integr. Syst., Vol. 10, No. 4. (August 2002), pp. 477-486. by Lan-Da Van posted to architecture vlsi by sugaya on 2007-08-07 09:45:22 as
	確率的ニューラルネットワーク計算の並列高速化アーキテクチャとその画像認識システムへの適用 [My Copy] 情報処理学会論文誌：ハイパフォーマンスコンピューティングシステム, Vol. 43, No. SIG 6(HPS 5). (September 2002), pp. 206-218. by 相部範之, 安永守利 posted to architecture neural vlsi by sugaya on 2007-08-07 09:43:02 as
	書き換え可能ハードウェアを用いた高速ホモロジー検索システム [My Copy] 情報処理学会論文誌：ハイパフォーマンスコンピューティングシステム, Vol. 43, No. SIG 6(HPS 5). (September 2002), pp. 196-205. by 山口佳樹, 宮島洋介, 丸山勉, 小長谷明彦 posted to architecture fpga by sugaya on 2007-08-07 09:40:24 as
	Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials [My Copy] IEEE Trans. Comput., Vol. 50, No. 5. (May 2001), pp. 385-393. by Chiou-Ying Lee, Erl-Huei Lu, Jau-Yien Lee posted to architecture systolic vlsi by sugaya on 2007-08-07 09:36:08 as
	A Systolic Image Difference Algorithm for RLE-Compressed Images [My Copy] IEEE Trans. Parallel Distrib. Syst., Vol. 11, No. 5. (May 2000), pp. 433-443. by Fikret Ercal, Mark Allen, Hao Feng posted to architecture systolic vlsi by sugaya on 2007-08-07 09:33:46 as
	A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms [My Copy] IEEE Trans. Comput., Vol. 49, No. 12. (December 2000), pp. 1297-1309. by Hyesook Lim, Vincenzo Piuri, Earl E. Swartzlander posted to architecture systolic vlsi by sugaya on 2007-08-07 09:31:47 as
	Two-ring systolic array network for artificial neural networks [My Copy] Circuits, Devices and Systems, IEE Proceedings - In Circuits, Devices and Systems, IEE Proceedings -, Vol. 146, No. 5. (1999), pp. 225-230. by H. Amin, K. M. Curtis, Hayes posted to architecture neural systolic vlsi by sugaya on 2007-08-07 09:29:30 as
	Efficient realizations of encoders and decoders based on the 2-D discrete wavelet transform [My Copy] IEEE Trans. Very Large Scale Integr. Syst., Vol. 7, No. 3. (September 1999), pp. 289-298. by Chaitali Chakrabarti, Clint Mumford posted to architecture vlsi by sugaya on 2007-08-07 09:26:33 as
	Parallel Implementation of Multidimensional Transforms without Interprocessor Communication [My Copy] IEEE Trans. Comput., Vol. 48, No. 9. (September 1999), pp. 951-961. by Francescomaria Marino, Earl E. Swartzlander posted to architecture systolic vlsi by sugaya on 2007-08-07 09:23:55 as
	Hyper-Systolic Parallel Computing [My Copy] IEEE Trans. Parallel Distrib. Syst., Vol. 9, No. 2. (February 1998), pp. 97-108. by Thomas Lippert, Klaus Schilling, Armin Seyfried, Achim Bode posted to architecture systolic by sugaya on 2007-08-07 09:21:20 as
	Optimal fault-tolerant design approach for VLSI array processors [My Copy] Computers and Digital Techniques, IEE Proceedings - In Computers and Digital Techniques, IEE Proceedings -, Vol. 144, No. 1. (1997), pp. 15-21. by C. N. Zhang, T. M. Bachtiar, W. K. Chou posted to architecture systolic vlsi by sugaya on 2007-08-07 09:18:40 as
	非同期並列処理系の設計開発支援システム [My Copy] 情報処理学会論文誌, Vol. 36, No. 4. (April 1995), pp. 1012-1022. by 佐藤健一, 阿曽弘具 posted to architecture systolic by sugaya on 2007-08-07 09:14:20 as
	Systolic modular multiplication [My Copy] IEEE Transactions on Computers In Transactions on Computers, Vol. 42, No. 3. (March 1993), pp. 376-378. by C. D. Walter posted to architecture systolic vlsi by sugaya on 2007-08-07 09:10:22 as
	多次元シストリックアレーの系統的設計法 [My Copy] 電子通信学会論文誌 D-I, Vol. J75-D-I, No. 9. (September 1992), pp. 879-881. by 小川誠治, 前場隆史, 阿部健一 posted to architecture systolic vlsi by sugaya on 2007-08-07 09:02:46 as
	On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication [My Copy] IEEE Trans. Comput., Vol. 40, No. 6. (June 1991), pp. 770-774. by Prasanna V. K. Kumar, Yu-Chen Tsai posted to architecture systolic vlsi by sugaya on 2007-08-07 08:59:31 as
	Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays [My Copy] IEEE Trans. Parallel Distrib. Syst., Vol. 1, No. 1. (January 1990), pp. 64-76. by P. Z. Lee, Z. M. Kedem posted to architecture systolic vlsi by sugaya on 2007-08-07 08:56:48 as
	On Systolic Contractions of Program Graphs [My Copy] IEEE Trans. Comput., Vol. 38, No. 10. (October 1989), pp. 1451-1457. by W. Shen, A. Y. Orau\cc posted to architecture systolic vlsi by sugaya on 2007-08-07 08:52:46 as
	A Family of New Efficient Arrays for Matrix Multiplication [My Copy] IEEE Trans. Comput., Vol. 38, No. 1. (January 1989), pp. 149-155. by H. V. Jagadish, T. Kailath posted to architecture systolic vlsi by sugaya on 2007-08-07 08:50:37 as
	正射影に基づくシストリックアルゴリズム設計手法 [My Copy] 電子通信学会論文誌 A, Vol. J71-A, No. 10. (October 1988), pp. 1878-1887. by 前場隆史, 辰巳昭治 posted to architecture systolic vlsi by sugaya on 2007-08-07 08:47:21 as
	シストリックアレーの自動設計法 [My Copy] Vol. J71-D, No. 8. (August 1988), pp. 1487-1495. by 阿曽弘具 posted to architecture systolic vlsi by sugaya on 2007-08-07 08:44:47 as
	シストリックアルゴリズムの定式化と情報の流れ [My Copy] 電子通信学会論文誌 D, Vol. J70-D, No. 6. (January 1987), pp. 1074-1082. by 阿曽弘具, 稲垣康善 posted to architecture systolic vlsi by sugaya on 2007-08-07 08:41:06 as
	Optimal graph algorithms on a fixed-size linear array [My Copy] IEEE Trans. Comput., Vol. 36, No. 4. (April 1987), pp. 460-470. by K. A. Doshi, P. J. Varman posted to architecture systolic vlsi by sugaya on 2007-08-07 08:36:17 as
	Systolic Arrays for Matrix Transpose and Other Reorderings [My Copy] IEEE Trans. Computers, Vol. 36, No. 1. (January 1987), pp. 117-122. by Dianne P. O'Leary posted to architecture systolic vlsi by sugaya on 2007-08-07 08:33:30 as
	ADVIS: A Software Package for the Design of Systolic Arrays [My Copy] IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems In Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 6, No. 1. (January 1987), pp. 33-40. by D. I. Moldovan posted to architecture systolic vlsi by sugaya on 2007-08-07 08:21:50 as
	Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays [My Copy] Transactions on Computers In Transactions on Computers, Vol. C-35, No. 1. (1986), pp. 1-12. by D. I. Moldovan, J. A. B. Fortes posted to architecture systolic vlsi by sugaya on 2007-08-07 08:18:53 as along with 1 person ceegrs2
	Polynomial Division on Systolic Arrays [My Copy] IEEE Trans. Computers, Vol. 34, No. 6. (June 1985), pp. 577-578. by Stanislav Zák, Kai Hwang posted to architecture systolic vlsi by sugaya on 2007-08-07 08:17:03 as
	On the design of algorithms for VLSI systolic arrays [My Copy] Proceedings of the IEEE In Proceedings of the IEEE, Vol. 71, No. 1. (1983), pp. 113-120. by D. I. Moldovan posted to architecture systolic vlsi by sugaya on 2007-08-07 08:05:08 as
	On the Analysis and Synthesis of VLSI Algorithms [My Copy] Transactions on Computers In Transactions on Computers, Vol. C-31, No. 11. (1982), pp. 1121-1126. by D. I. Moldovan posted to architecture systolic vlsi by sugaya on 2007-08-07 08:03:38 as
	Efficient Query Evaluation on Large Textual Collections in a Peer-to-Peer Environment [My Copy] In P2P '05: Proceedings of the Fifth IEEE International Conference on Peer-to-Peer Computing (P2P'05) (2005), pp. 225-233. by Jiangong Zhang, Torsten Suel posted to grid p2p by sugaya on 2007-07-23 08:59:29 as
	An Instance-based Learning Approach for Predicting Execution Times [My Copy] In Third International Information and Telecommunication Technologies Symposium (2004) by Luciano J. Senger, Marcos J. Santana posted to runtime-prediction scheduling by sugaya on 2007-07-09 07:36:45 as
	Predicting Run Times of Applications Using Rough Sets [My Copy] In 9th International Conf. on Information Processing and Management of Uncertainty in Knowledge-Based Systems (2002), pp. 455-462. by Shonali Krishnaswamy, Arkady Zaslavsky, Seng W. Loke posted to parallel runtime-prediction scheduling by sugaya on 2007-07-03 09:28:09 as
	Market-Based Resource Allocation for Grid Computing: A Model and Simulation [My Copy] (2003) by J. Gomoluch, M. Schroeder posted to grid market-based scheduling task-mapping by sugaya on 2007-06-25 09:36:51 as
	The organic grid: self-organizing computation on a peer-to-peer network [My Copy] Autonomic Computing, 2004. Proceedings. International Conference on (2004), pp. 96-103. by A. J. Chakravarti, G. Baumgartner, M. Lauria posted to grid master-slave scheduling by sugaya on 2007-06-18 07:29:25 as along with 2 people and 1 group jvdh broussea Rigi
	Allocating task interaction graphs to processors in heterogeneous networks [My Copy] Parallel and Distributed Systems, IEEE Transactions on, Vol. 8, No. 9. (September 1997), pp. 908-925. by Chi-Chung Hui, S. T. Chanson posted to mapping parallel tig by sugaya on 2007-06-05 12:43:46 as
	Optimal task assignment in homogeneous networks [My Copy] Parallel and Distributed Systems, IEEE Transactions on, Vol. 8, No. 2. (February 1997), pp. 119-129. by Cheol-Hoon Lee, K. G. Shin posted to mapping parallel tig by sugaya on 2007-06-05 12:33:31 as
	Fast allocation of processes in distributed and parallel systems [My Copy] Parallel and Distributed Systems, IEEE Transactions on, Vol. 4, No. 2. (February 1993), pp. 164-174. by C. M. Woodside, G. G. Monforton posted to bin-packing mapping parallel tig by sugaya on 2007-06-05 12:26:08 as
	On the assignment problem of arbitrary process systems to heterogeneous distributed computer systems [My Copy] Transactions on Computers, Vol. 41, No. 3. (1992), pp. 257-273. by N. S. Bowen, C. N. Nikolaou, A. Ghafoor posted to mapping parallel tig by sugaya on 2007-06-05 12:21:50 as
	Optimal task assignment in linear array networks [My Copy] Transactions on Computers, Vol. 41, No. 7. (1992), pp. 877-880. by Cheol-Hoon Lee, Dongmyun Lee, Myunghwan Kim posted to mapping parallel tig by sugaya on 2007-06-05 12:17:38 as
	On the Complexity of Scheduling Problems for Parallel/Pipelined Machines [My Copy] IEEE Trans. Comput., Vol. 38, No. 9. (September 1989), pp. 1308-1313. by David Bernstein, Michael Rodeh, Izidor Gertner posted to parallel scheduling tig by sugaya on 2007-06-05 12:14:13 as
	Heuristic algorithms for task assignment in distributed systems [My Copy] Computers, IEEE Transactions on, Vol. 37, No. 11. (1988), pp. 1384-1397. by V. Lo posted to mapping parallel tig by sugaya on 2007-06-05 12:10:32 as
	A taxonomy of scheduling in general-purpose distributed computing systems [My Copy] IEEE Trans. Software Eng., Vol. 14, No. 2. (February 1988), pp. 141-154. by T. L. Casavant, J. G. Kuhl posted to parallel scheduling tig by sugaya on 2007-06-05 12:06:11 as along with 3 people jvdh chiayung smithmc
	Load Redistribution Under Failure in Distributed Systems [My Copy] Transactions on Computers, Vol. C-32, No. 9. (September 1983), pp. 799-808. by T. C. K. Chou, J. A. Abraham posted to fault-tolerant mapping parallel by sugaya on 2007-06-05 12:03:38 as
	An Application of Bin-Packing to Multiprocessor Scheduling [My Copy] SIAM Journal on Computing, Vol. 7, No. 1. (February 1978), pp. 1-17. by E. G. Coffman_jr, M. R. Garey, D. S. Johnson posted to mapping parallel tig by sugaya on 2007-06-05 11:40:13 as along with 2 people mrt2k9 babak146
	Multiprocessor Scheduling with the Aid of Network Flow Algorithms [My Copy] Software Engineering, IEEE Transactions on, Vol. SE-3, No. 1. (January 1977), pp. 85-93. by H. S. Stone posted to mapping network-flow parallel scheduling tig by sugaya on 2007-06-05 11:31:29 as
	Task Allocation by Parallel Evolutionary Computing [My Copy] Journal of Parallel and Distributed Computing, Vol. 47 (1997), pp. 91-97. by A. Schoneveld, P. M. A. Sloot posted to ga mapping parallel sa by sugaya on 2007-06-05 11:27:49 as
	Taskgraph mapping using a genetic algorithm: A comparison of fitness functions [My Copy] Parallel Computing, Vol. 19 (November 1993), pp. 1313-1317. by S. Hurley posted to ga mapping parallel tig by sugaya on 2007-06-05 11:27:48 as
	Heuristic Models of Task Assignment Scheduling in Distributed Systems [My Copy] Computer, Vol. 15 (June 1982), pp. 50-56. by K. Efe posted to mapping parallel tig by sugaya on 2007-06-05 11:27:47 as

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parallel	52
architecture	36
vlsi	28
systolic	24
scheduling	20
para-alg	14
tig	13
mapping	12
algorithm	12
ga	11
compiler	9
tpg	9
grid	8
svm	7
p2p	6
neural	4
mpi	3
petri-net	3
graph	2
master-slave	2
runtime-prediction	2
programming	2
pvm	2
ninf	2
shared-memory	2
task-mapping	2
simd	1
coherence	1
openmp	1
ldpc	1
multi-grain	1
lapack	1
data-grid	1
blas	1
tool	1
fpga	1
network-flow	1
agent	1
manual	1
fault-tolerant	1
cache	1
cg	1
lam	1
market-based	1
jpeg	1
network	1
bin-packing	1
sa	1

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