Ultra-low power digital subthreshold logic circuits Export

@inproceedings{citeulike:423797, abstract = {Numerous efforts in balancing the trade-off between power, area and performance have been done in the medium performance, medium power region of the design spectrum. However, not much study has been done at the two extreme ends of the design spectrum, namely the ultra-low power with acceptable performance at one end (the focus of this paper), and high performance with power within limit at the other. One solution to achieve the ultra-low power requirement is to operate the digital logic gates in the subthreshold region. We analyze both CMOS and Pseudo-NMOS logic families operating in the subthreshold region. We compare the results with CMOS in the normal strong inversion region and with other known low-power logic, namely, energy recovery logic. Our results show an energy per switching reduction of two orders of magnitude for an 8/spl times/8 carry save array multiplier when it is operated in the subthreshold region.}, author = {Soeleman, H. and Roy, K.}, citeulike-article-id = {423797}, citeulike-linkout-0 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=799418}, journal = {Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on}, keywords = {circuits, digital, logic, ultra-low-power}, pages = {94--96}, posted-at = {2005-12-06 23:48:52}, priority = {4}, title = {Ultra-low power digital subthreshold logic circuits}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=799418}, year = {1999} }

TY - CONF ID - citeulike:423797 L3 - citeulike-article-id:423797 N2 - Numerous efforts in balancing the trade-off between power, area and performance have been done in the medium performance, medium power region of the design spectrum. However, not much study has been done at the two extreme ends of the design spectrum, namely the ultra-low power with acceptable performance at one end (the focus of this paper), and high performance with power within limit at the other. One solution to achieve the ultra-low power requirement is to operate the digital logic gates in the subthreshold region. We analyze both CMOS and Pseudo-NMOS logic families operating in the subthreshold region. We compare the results with CMOS in the normal strong inversion region and with other known low-power logic, namely, energy recovery logic. Our results show an energy per switching reduction of two orders of magnitude for an 8/spl times/8 carry save array multiplier when it is operated in the subthreshold region. JF - Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on EP - 96 TI - Ultra-low power digital subthreshold logic circuits SP - 94 KW - circuits KW - digital KW - logic KW - ultra-low-power AU - Soeleman, H AU - Roy, K PY - 1999/// UR - http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=799418 ER -