Ultra-low-power CMOS technologies Export

@inproceedings{citeulike:423800, abstract = {The fast growing portable-electronics market as well as thermal dissipation, reliability, and scalability issues have launched a massive trend towards low-power and low-voltage technologies. This has lead to a new, reduced standard digital CMOS supply voltage of 3.3 V reducing the power consumption by 70\%. However, the power consumption can still be cut down substantially by reducing the supply and threshold voltages much further without compromising systems performance. A loss in device speed can be compensated on the systems level by appropriate parallel architectures. Based on this concept of ultra-low-power CMOS technologies we explore the lower limits of CMOS supply voltage and switching energy for a variety of circuit classes analytically and numerically. Ultra-low-power (ULP) process and device design, device modeling, performance evaluation, and the specific problems associated with ULP mixed-analog-digital technologies are discussed}, author = {Schrom, G. and Selberherr, S.}, citeulike-article-id = {423800}, citeulike-linkout-0 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=557352}, journal = {Semiconductor Conference, 1996., International}, keywords = {cmos, ultra-low-power}, pages = {237--246 vol.1}, posted-at = {2005-12-06 23:52:41}, priority = {4}, title = {Ultra-low-power CMOS technologies}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=557352}, volume = {1}, year = {1996} }

TY - CONF ID - citeulike:423800 L3 - citeulike-article-id:423800 N2 - The fast growing portable-electronics market as well as thermal dissipation, reliability, and scalability issues have launched a massive trend towards low-power and low-voltage technologies. This has lead to a new, reduced standard digital CMOS supply voltage of 3.3 V reducing the power consumption by 70%. However, the power consumption can still be cut down substantially by reducing the supply and threshold voltages much further without compromising systems performance. A loss in device speed can be compensated on the systems level by appropriate parallel architectures. Based on this concept of ultra-low-power CMOS technologies we explore the lower limits of CMOS supply voltage and switching energy for a variety of circuit classes analytically and numerically. Ultra-low-power (ULP) process and device design, device modeling, performance evaluation, and the specific problems associated with ULP mixed-analog-digital technologies are discussed JF - Semiconductor Conference, 1996., International EP - 246 vol.1 TI - Ultra-low-power CMOS technologies VL - 1 SP - 237 KW - cmos KW - ultra-low-power AU - Schrom, G AU - Selberherr, S PY - 1996/// UR - http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=557352 ER -