High-performance NMOS operational amplifier Export

@article{citeulike:906031, abstract = {A high performance operational amplifier 300 mil/SUP 2/ in area has been designed and fabricated in a standard n-channel silicon-gate enhancement/depletion MOS process. Specifications achieved include open-loop gain, 1000; power consumption, 10 mW; common-mode range within 1.5 V of either supply rail; unity-gain bandwidth, 3.0 MHz with 80/spl deg/ phase margin; RMS input noise (2.5 Hz-46 kHz), 25 /spl mu/V; C-message weighted noise -5 dBrnC; and 0.1-percent settling time, 2.5 /spl mu/s.}, author = {Senderowicz, D. and Hodges, D. A. and Gray, P. R.}, citeulike-article-id = {906031}, citeulike-linkout-0 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1052047}, journal = {Solid-State Circuits, IEEE Journal of}, keywords = {amplifier, depletion, mode}, number = {6}, pages = {760--766}, posted-at = {2006-10-19 16:56:08}, priority = {2}, title = {High-performance NMOS operational amplifier}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1052047}, volume = {13}, year = {1978} }

TY - JOUR ID - citeulike:906031 L3 - citeulike-article-id:906031 N2 - A high performance operational amplifier 300 mil/SUP 2/ in area has been designed and fabricated in a standard n-channel silicon-gate enhancement/depletion MOS process. Specifications achieved include open-loop gain, 1000; power consumption, 10 mW; common-mode range within 1.5 V of either supply rail; unity-gain bandwidth, 3.0 MHz with 80/spl deg/ phase margin; RMS input noise (2.5 Hz-46 kHz), 25 /spl mu/V; C-message weighted noise -5 dBrnC; and 0.1-percent settling time, 2.5 /spl mu/s. IS - 6 JF - Solid-State Circuits, IEEE Journal of EP - 766 TI - High-performance NMOS operational amplifier VL - 13 SP - 760 KW - amplifier KW - depletion KW - mode AU - Senderowicz, D AU - Hodges, DA AU - Gray, PR PY - 1978/// UR - http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1052047 ER -