A high-speed logic LSI using diffusion self-aligned enhancement depletion MOST Export

@inproceedings{citeulike:907106, abstract = {Sub-nanosecond, sub-picojoule gates with standard photolithographic technology have been realized using a DSAED-MOS ring oscillator. This paper will describe a high-speed (2.9 ns/2pJ) logic LSI, using this unit gate design.}, author = {Ohta, K. and Morimoto, M. and Saitoh, M. and Fukuda, T. and Morino, A. and Shimizu, K. and Hayashi, Y. and Tarui, Y.}, citeulike-article-id = {907106}, citeulike-linkout-0 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1155361}, journal = {Solid-State Circuits Conference. Digest of Technical Papers. 1975 IEEE International}, keywords = {depletion, logic, mode}, pages = {124--125}, posted-at = {2006-10-19 20:53:37}, priority = {2}, title = {A high-speed logic LSI using diffusion self-aligned enhancement depletion MOST}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1155361}, volume = {XVIII}, year = {1975} }

TY - CONF ID - citeulike:907106 L3 - citeulike-article-id:907106 N2 - Sub-nanosecond, sub-picojoule gates with standard photolithographic technology have been realized using a DSAED-MOS ring oscillator. This paper will describe a high-speed (2.9 ns/2pJ) logic LSI, using this unit gate design. JF - Solid-State Circuits Conference. Digest of Technical Papers. 1975 IEEE International EP - 125 TI - A high-speed logic LSI using diffusion self-aligned enhancement depletion MOST VL - XVIII SP - 124 KW - depletion KW - logic KW - mode AU - Ohta, K AU - Morimoto, M AU - Saitoh, M AU - Fukuda, T AU - Morino, A AU - Shimizu, K AU - Hayashi, Y AU - Tarui, Y PY - 1975/// UR - http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1155361 ER -