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Embedded floating-point units in FPGAs

by: Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert
In Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays (2006), pp. 12-20, doi:10.1145/1117201.1117204  Key: citeulike:671495

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Abstract

Due to their generic and highly programmable nature, FPGAs provide the ability to implement a wide range of applications. However, it is this nonspecific nature that has limited the use of FPGAs in scientific applications that require floating-point arithmetic. Even simple floating-point operations consume a large amount of computational resources. In this paper, we introduce embedding floating-point multiply-add units in an island style FPGA. This has shown to have an average area savings of 55.0% and an average increase of 40.7% in clock rate over existing architectures.


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