3D Integration of CMOS transistors with ICV-SLID technology Export

@article{116, abstract = {3D Integration of CMOS transistors with ICV-SLID technology is reported in this paper. NMOS and PMOS metal gate transistor devices have been further processed by forming deep trench inter-chip-vias and by thinning the substrate to 25 [mu]m remaining silicon thickness. No degradation of transistor behavior found due to the additional 3d-processing steps. Results of the process flow and electrical measurements of transistors on thin silicon are shown in this paper.}, author = {Wieland, Robert and Bonfert, Detlef and Klumpp, Armin and Merkel, Reinhard and Nebrich, Lars and Weber, Josef and Ramm, Peter}, booktitle = {Proceedings of the ninth european workshop on materials for advanced metallization 2005}, citeulike-article-id = {2797383}, citeulike-linkout-0 = {http://dx.doi.org/10.1016/j.mee.2005.07.052}, citeulike-linkout-1 = {http://www.sciencedirect.com/science/article/B6V0W-4GX6G3V-2/1/330795121d98215e6aeb84b6f2bd2cc2}, doi = {10.1016/j.mee.2005.07.052}, journal = {Microelectronic Engineering}, keywords = {3d-integration, cmos, microelectronics}, month = {December}, number = {3-4}, pages = {529--533}, posted-at = {2008-05-14 11:38:36}, priority = {2}, title = {3D Integration of CMOS transistors with ICV-SLID technology}, url = {http://dx.doi.org/10.1016/j.mee.2005.07.052}, volume = {82}, year = {2005} }

TY - JOUR ID - 116 L3 - citeulike-article-id:2797383 N2 - 3D Integration of CMOS transistors with ICV-SLID technology is reported in this paper. NMOS and PMOS metal gate transistor devices have been further processed by forming deep trench inter-chip-vias and by thinning the substrate to 25 [mu]m remaining silicon thickness. No degradation of transistor behavior found due to the additional 3d-processing steps. Results of the process flow and electrical measurements of transistors on thin silicon are shown in this paper. IS - 3-4 JF - Microelectronic Engineering EP - 533 TI - 3D Integration of CMOS transistors with ICV-SLID technology VL - 82 T2 - Proceedings of the ninth european workshop on materials for advanced metallization 2005 SP - 529 KW - 3d-integration KW - cmos KW - microelectronics AU - Wieland, Robert AU - Bonfert, Detlef AU - Klumpp, Armin AU - Merkel, Reinhard AU - Nebrich, Lars AU - Weber, Josef AU - Ramm, Peter PY - 2005/12// UR - http://dx.doi.org/10.1016/j.mee.2005.07.052 ER -