Reliable tantalum-gate fully-depleted-SOI MOSFET technology featuring low-temperature processing

@article{123, abstract = {A reliable tantalum (Ta)-gate device technology, which can drastically reduce the number of process steps, has been developed. Ta-gate fully-depleted-silicon-on-insulator (FDSOI) MOSFETs with 0.15-μm gate length by low-temperature processing below 500°C after the gate oxide formation have good on/off characteristics. Comprehensive design guidelines for Ta-gate MOSFETs in the deep-submicrometer regime is provided by investigating a wide range of performance and reliability constraints on the process temperature and the SOI thickness. In the guideline, the recrystallization of the source/drain region gives inferior limits of the SOI thickness and the process temperature. Thermal reaction between Ta and SiO₂ films sets a superior limit of the process temperature, and a short-channel effect sets a superior limit of the SOI thickness}, author = {Ushiki, T. and Yu, Mo-Chiun and Hirano, Y. and Shimada, H. and Morita, M. and Ohmi, T. }, booktitle = {Electron Devices, IEEE Transactions on}, citeulike-article-id = {2815401}, doi = {http://dx.doi.org/10.1109/16.622603}, journal = {IEEE Transactions on Electron Devices}, keywords = {gate, introduction, metal, metal-gate, resistivity}, number = {9}, pages = {1467--1472}, posted-at = {2008-05-20 10:02:41}, priority = {2}, title = {Reliable tantalum-gate fully-depleted-SOI MOSFET technology featuring low-temperature processing}, url = {http://dx.doi.org/10.1109/16.622603}, volume = {44}, year = {1997} }

TY - JOUR ID - 123 L3 - citeulike-article-id:2815401 TI - Reliable tantalum-gate fully-depleted-SOI MOSFET technology featuring low-temperature processing T2 - Electron Devices, IEEE Transactions on JF - IEEE Transactions on Electron Devices VL - 44 IS - 9 SP - 1467 EP - 1472 N2 - A reliable tantalum (Ta)-gate device technology, which can drastically reduce the number of process steps, has been developed. Ta-gate fully-depleted-silicon-on-insulator (FDSOI) MOSFETs with 0.15-μm gate length by low-temperature processing below 500°C after the gate oxide formation have good on/off characteristics. Comprehensive design guidelines for Ta-gate MOSFETs in the deep-submicrometer regime is provided by investigating a wide range of performance and reliability constraints on the process temperature and the SOI thickness. In the guideline, the recrystallization of the source/drain region gives inferior limits of the SOI thickness and the process temperature. Thermal reaction between Ta and SiO₂ films sets a superior limit of the process temperature, and a short-channel effect sets a superior limit of the SOI thickness KW - gate KW - introduction KW - metal KW - metal-gate KW - resistivity AU - Ushiki, T AU - Yu, Mo-Chiun AU - Hirano, Y AU - Shimada, H AU - Morita, M AU - Ohmi, T PY - 1997/// UR - http://dx.doi.org/10.1109/16.622603 ER -