CMOS scaling into the nanometer regime Export

@article{124, abstract = {Starting with a brief review on 0.1-μm (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling}, author = {Taur, Yuan and Buchanan, D. A. and Chen, Wei and Frank, D. J. and Ismail, K. E. and Lo, Shih-Hsien and Sai-Halasz, G. A. and Viswanathan, R. G. and Wann, H. J. C. and Wind, S. J. and Wong, Hon-Sum}, booktitle = {Proceedings of the IEEE}, citeulike-article-id = {2815408}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/5.573737}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=573737}, day = {06}, doi = {10.1109/5.573737}, journal = {Proceedings of the IEEE}, keywords = {capacitive, gate, introduction, metal}, month = {August}, number = {4}, pages = {486--504}, posted-at = {2008-05-20 10:04:37}, priority = {2}, title = {CMOS scaling into the nanometer regime}, url = {http://dx.doi.org/10.1109/5.573737}, volume = {85}, year = {2002} }

TY - JOUR ID - 124 L3 - citeulike-article-id:2815408 N2 - Starting with a brief review on 0.1-μm (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling IS - 4 JF - Proceedings of the IEEE EP - 504 TI - CMOS scaling into the nanometer regime VL - 85 T2 - Proceedings of the IEEE SP - 486 KW - capacitive KW - gate KW - introduction KW - metal AU - Taur, Yuan AU - Buchanan, DA AU - Chen, Wei AU - Frank, DJ AU - Ismail, KE AU - Lo, Shih-Hsien AU - Sai-Halasz, GA AU - Viswanathan, RG AU - Wann, HJC AU - Wind, SJ AU - Wong, Hon-Sum PY - 2002/08/06/ UR - http://dx.doi.org/10.1109/5.573737 ER -