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30 nm Tungsten gates etched by a low damage ICP etching for the fabrication of compound semiconductor transistors

Microelectronic Engineering In Micro- and Nano-Engineering MNE 2005, Vol. 83, No. 4-9. ( 2006), pp. 1152-1154.

by X. Li, X. Cao, H. Zhou, et al.C. D. W. Wilkinson, S. Thoms, D. Macintyre, M. Holland, I. G. Thayne

posted to c4f8 etching icp sf6 tungsten by these_morel on 2006-07-26 12:51:56 as read

along with 1 person Stanley_vrc

A low damage RIE process for the fabrication of compound semiconductor based transistors with sub-100 nm tungsten gates

Microelectronic Engineering In Micro- and Nano-Engineering MNE 2005, Vol. 83, No. 4-9. ( 2006), pp. 1159-1162.

by X. Li, X. Cao, H. Zhou, et al.C. D. W. Wilkinson, S. Thoms, D. Macintyre, M. Holland, I. G. Thayne

posted to etching rie sf6-chf3 sf6-n2 sf6-o2 tungsten by these_morel on 2006-06-19 09:36:54 as read

along with 1 person Stanley_vrc

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plasma	54
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introduction	46
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dispositifs-experimentaux	26
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