A scalable approach to thread-level speculation Export

@article{citeulike:270927, abstract = {While architects understand how to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the real challenge is how to easily create parallel software to effectively exploit all of this raw performance potential. One promising technique for overcoming this problem is Thread-Level Speculation (TLS), which enables the compiler to optimistically create parallel threads despite uncertainty as to whether those threads are actually independent. In this paper, we propose and evaluate a design for supporting TLS that seamlessly scales to any machine size because it is a straightforward extension of writeback invalidation-based cache coherence (which itself scales both up and down). Our experimental results demonstrate that our scheme performs well on both single-chip multiprocessors and on larger-scale machines where communication latencies are twenty times larger.}, address = {New York, NY, USA}, author = {Steffan, J. Greggory and Colohan, Christopher B. and Zhai, Antonia and Mowry, Todd C.}, booktitle = {ISCA '00: Proceedings of the 27th annual international symposium on Computer architecture}, citeulike-article-id = {270927}, citeulike-linkout-0 = {http://portal.acm.org/citation.cfm?id=339650}, citeulike-linkout-1 = {http://dx.doi.org/10.1145/339647.339650}, doi = {10.1145/339647.339650}, issn = {0163-5964}, journal = {SIGARCH Comput. Archit. News}, keywords = {ece396}, month = {May}, number = {2}, pages = {1--12}, posted-at = {2007-05-15 23:03:53}, priority = {2}, publisher = {ACM}, title = {A scalable approach to thread-level speculation}, url = {http://dx.doi.org/10.1145/339647.339650}, volume = {28}, year = {2000} }

TY - JOUR ID - citeulike:270927 L3 - citeulike-article-id:270927 N2 - While architects understand how to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the real challenge is how to easily create parallel software to effectively exploit all of this raw performance potential. One promising technique for overcoming this problem is Thread-Level Speculation (TLS), which enables the compiler to optimistically create parallel threads despite uncertainty as to whether those threads are actually independent. In this paper, we propose and evaluate a design for supporting TLS that seamlessly scales to any machine size because it is a straightforward extension of writeback invalidation-based cache coherence (which itself scales both up and down). Our experimental results demonstrate that our scheme performs well on both single-chip multiprocessors and on larger-scale machines where communication latencies are twenty times larger. IS - 2 JF - SIGARCH Comput. Archit. News SN - 0163-5964 AD - New York, NY, USA EP - 12 TI - A scalable approach to thread-level speculation PB - ACM VL - 28 T2 - ISCA '00: Proceedings of the 27th annual international symposium on Computer architecture SP - 1 KW - ece396 AU - Steffan, Greggory AU - Colohan, Christopher AU - Zhai, Antonia AU - Mowry, Todd PY - 2000/05// UR - http://dx.doi.org/10.1145/339647.339650 ER -