Process optimization of lead-free wafer-level underfill material used in chip scale packaging

@inproceedings{citeulike:1453711, abstract = {Wafer-level underfilling is an emerging technology that consists of pre-applying the underfill material on wafer during the wafer fabrication process. The novel underfill material and the process enable the chip manufacturers to perform underfill at the wafer-level, thereby eliminating multiple steps in the packaging process and cutting production cost significantly. However, lead-free solder poses significant challenge to this new technology. Compared to eutectic solder, lead-free solder tends to have a lower yield stress, requires higher reflow temperature and forms brittle joints. With increasing demand of lead-free compatible packaging material, further advancement of wafer level underfill material and process optimization are necessary to ensure compatibility with lead-free solders, better voiding performance and higher interconnection yield. We have developed novel wafer level underfill materials for chip scale packaging that are compatible with lead-free assembly. These materials, when coated on the wafer, form clear, transparent coating after B-stage that can be diced into coated dies without any delaminating and cracking. In this paper we discuss the effect of various heating profiles and different equipment used in the B-stage step on flow of underfill during the reflow, residual solvent after B-stage, solder paste smearing, and interconnection yield. By optimizing the material properties and B-stage conditions, we demonstrated that wafer level underfill material can achieve high interconnect yield without causing smearing and voiding in lead-free assembly.}, author = {Liu, Y. and Dutt, G. and Xiao, A. }, citeulike-article-id = {1453711}, doi = {http://dx.doi.org/10.1109/ISAPM.2005.1432092}, journal = {Advanced Packaging Materials: Processes, Properties and Interfaces, 2005. Proceedings. International Symposium on}, keywords = {lead-free}, pages = {293--297}, posted-at = {2007-07-13 10:52:59}, priority = {2}, title = {Process optimization of lead-free wafer-level underfill material used in chip scale packaging}, url = {http://dx.doi.org/10.1109/ISAPM.2005.1432092}, year = {2005} }

TY - CONF ID - citeulike:1453711 L3 - citeulike-article-id:1453711 TI - Process optimization of lead-free wafer-level underfill material used in chip scale packaging JF - Advanced Packaging Materials: Processes, Properties and Interfaces, 2005. Proceedings. International Symposium on SP - 293 EP - 297 N2 - Wafer-level underfilling is an emerging technology that consists of pre-applying the underfill material on wafer during the wafer fabrication process. The novel underfill material and the process enable the chip manufacturers to perform underfill at the wafer-level, thereby eliminating multiple steps in the packaging process and cutting production cost significantly. However, lead-free solder poses significant challenge to this new technology. Compared to eutectic solder, lead-free solder tends to have a lower yield stress, requires higher reflow temperature and forms brittle joints. With increasing demand of lead-free compatible packaging material, further advancement of wafer level underfill material and process optimization are necessary to ensure compatibility with lead-free solders, better voiding performance and higher interconnection yield. We have developed novel wafer level underfill materials for chip scale packaging that are compatible with lead-free assembly. These materials, when coated on the wafer, form clear, transparent coating after B-stage that can be diced into coated dies without any delaminating and cracking. In this paper we discuss the effect of various heating profiles and different equipment used in the B-stage step on flow of underfill during the reflow, residual solvent after B-stage, solder paste smearing, and interconnection yield. By optimizing the material properties and B-stage conditions, we demonstrated that wafer level underfill material can achieve high interconnect yield without causing smearing and voiding in lead-free assembly. KW - lead-free AU - Liu, Y AU - Dutt, G AU - Xiao, A PY - 2005/// UR - http://dx.doi.org/10.1109/ISAPM.2005.1432092 ER -