A tightly coupled finite field arithmetic hardware in an FPGA-based embedded processor core for elliptic curve cryptography Export

@proceedings{Khalil1, abstract = {This work presents the implementation of a tightly-coupled hardware architectural enhancement to the Altera FPGA-based Nios II embedded processor. The goal is to accelerate finite field arithmetic operations in the binary fields of F₂ ¹⁶³ and F₂ ¹⁹³, for application in a high-performance embedded system implementing elliptic-curve cryptography (ECC). The concept is to augment the embedded processor with a few custom instructions for fast finite field arithmetic operations. Instead of a co-processor, hardware acceleration of the arithmetic operation is provided by custom logic tightly coupled to the processor core and directly controlled by the instruction stream. This concept, which may be considered as a hardware-software codesign approach, is evaluated by prototyping an elliptic curve cryptosystem (ECC) on an Altera Stratix FPGA development board. Experimental results show that for the point multiplication operation, which is the core operation in an ECC computation, the implementation with custom instructions and tightly-coupled hardware is about 50\% faster than the coprocessor based hardware.}, author = {Khalil-Hani, M. and Irwansyah, A. and Hau, Y. W.}, booktitle = {Electronic Design, 2008. ICED 2008. International Conference on}, citeulike-article-id = {5217605}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/ICED.2008.4786692}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4786692}, doi = {10.1109/ICED.2008.4786692}, journal = {Electronic Design, 2008. ICED 2008. International Conference on}, keywords = {ecc}, pages = {1--6}, posted-at = {2009-07-21 11:06:30}, priority = {0}, title = {A tightly coupled finite field arithmetic hardware in an FPGA-based embedded processor core for elliptic curve cryptography}, url = {http://dx.doi.org/10.1109/ICED.2008.4786692}, year = {2008} }

TY - CONF ID - Khalil1 L3 - citeulike-article-id:5217605 N2 - This work presents the implementation of a tightly-coupled hardware architectural enhancement to the Altera FPGA-based Nios II embedded processor. The goal is to accelerate finite field arithmetic operations in the binary fields of F₂ ¹⁶³ and F₂ ¹⁹³, for application in a high-performance embedded system implementing elliptic-curve cryptography (ECC). The concept is to augment the embedded processor with a few custom instructions for fast finite field arithmetic operations. Instead of a co-processor, hardware acceleration of the arithmetic operation is provided by custom logic tightly coupled to the processor core and directly controlled by the instruction stream. This concept, which may be considered as a hardware-software codesign approach, is evaluated by prototyping an elliptic curve cryptosystem (ECC) on an Altera Stratix FPGA development board. Experimental results show that for the point multiplication operation, which is the core operation in an ECC computation, the implementation with custom instructions and tightly-coupled hardware is about 50% faster than the coprocessor based hardware. JF - Electronic Design, 2008. ICED 2008. International Conference on EP - 6 TI - A tightly coupled finite field arithmetic hardware in an FPGA-based embedded processor core for elliptic curve cryptography T2 - Electronic Design, 2008. ICED 2008. International Conference on SP - 1 KW - ecc AU - Khalil-Hani, M AU - Irwansyah, A AU - Hau, YW PY - 2008/// UR - http://dx.doi.org/10.1109/ICED.2008.4786692 ER -