walteryhli's library 94 articles Export

	Architecture and Evaluation of an Asynchronous Array of Simple Processors [My Copy] Journal of Signal Processing Systems, Vol. 53, No. 3. (1 December 2008), pp. 243-259. by Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, et al.Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Tinoosh Mohsenin, Bevan Baas posted to data-level-parallelism chip-multiprocessors by walteryhli on 2009-11-29 12:32:40 as
	An asynchronous array of simple processors for dsp applications [My Copy] Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International (9 February 2006), pp. 1696-1705. by Zhiyi Yu, M. Meeuwsen, R. Apperson, et al.O. Sattari, M. Lai, J. Webb, E. Work, T. Mohsenin, M. Singh, B. Baas posted to data-level-parallelism chip-multiprocessors by walteryhli on 2009-11-29 10:29:49 as
	From Specification to High-Volume Production [My Copy] Design & Test of Computers, IEEE, Vol. 26, No. 2. (24 April 2009), pp. 30-33. by M. d'Abreu posted to soc-project-management by walteryhli on 2009-11-20 14:58:08 as
	Case Study of a 65-nm SoC Design [My Copy] Design & Test of Computers, IEEE, Vol. 26, No. 2. (24 April 2009), pp. 14-19. by A. Chang posted to soc-project-management by walteryhli on 2009-11-20 14:38:21 as
	The Story behind the Intel Atom Processor Success [My Copy] IEEE Des. Test, Vol. 26, No. 2. (2009), pp. 8-13. by Brad Beavers posted to soc-project-management by walteryhli on 2009-11-20 13:57:12 as
	An integrated platform of collaborative project management and silicon intellectual property management for IC design industry [My Copy] Information Sciences, Vol. 179, No. 15. (04 July 2009), pp. 2576-2590. by David W. Hsiao, Amy J. C. Trappey, Lin Ma, Pei-Shun Ho posted to soc-project-management by walteryhli on 2009-11-20 13:54:45 as
	iCFP: Tolerating all-level cache misses in in-order processors [My Copy] High Performance Computer Architecture, 2009. HPCA 2009. IEEE 15th International Symposium on (06 March 2009), pp. 431-442. by A. Hilton, S. Nagarakatte, A. Roth posted to runahead-execution by walteryhli on 2009-11-10 15:18:53 as
	Dynamic heterogeneity and the need for multicore virtualization [My Copy] SIGOPS Oper. Syst. Rev., Vol. 43, No. 2. (2009), pp. 5-14. by Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi posted to manycore-os by walteryhli on 2009-10-29 18:14:46 as
	Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications [My Copy] In HPCA '07: Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture (2007), pp. 25-36. by Hongtao Zhong, Steven A. Lieberman, Scott A. Mahlke posted to core-fusion by walteryhli on 2009-10-29 18:02:51 as along with 2 people anshumangupta dhjeon
	Federation: Out-of-Order Execution using Simple In-Order Cores [My Copy] (August 2007) by David Tarjan, Michael Boyer, Kevin Skadron posted to core-fusion by walteryhli on 2009-10-29 17:51:32 as
	Multitasking workload scheduling on flexible-core chip multiprocessors [My Copy] In PACT '08: Proceedings of the 17th international conference on Parallel architectures and compilation techniques (2008), pp. 187-196. by Divya P. Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger posted to manycore-os by walteryhli on 2009-10-29 17:15:34 as
	The Impact of Performance Asymmetry in Emerging Multicore Architectures [My Copy] In ISCA '05: Proceedings of the 32nd annual international symposium on Computer Architecture (2005), pp. 506-517. by Saisanthosh Balakrishnan, Ravi Rajwar, Mike Upton, Konrad Lai posted to manycore-os by walteryhli on 2009-10-29 17:08:24 as along with 3 people elsaturnino mitake Gnurou
	Fast switching of threads between cores [My Copy] SIGOPS Oper. Syst. Rev., Vol. 43, No. 2. (2009), pp. 35-45. by Richard Strong, Jayaram Mudigonda, Jeffrey C. Mogul, Nathan Binkert, Dean Tullsen posted to manycore-os by walteryhli on 2009-10-29 17:05:48 as
	Dynamic thread assignment on heterogeneous multiprocessor architectures [My Copy] In CF '06: Proceedings of the 3rd conference on Computing frontiers (2006), pp. 29-40. by Michela Becchi, Patrick Crowley posted to manycore-os by walteryhli on 2009-10-29 17:01:03 as
	Operating System Support for Shared-ISA Asymmetric Multi-core Architectures [My Copy] In Proceedings of the Fourth Annual Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA '08) (June 2008), pp. 19-26. by Tong Li, Paul Brett, Barbara Hohlt, Rob Knauerhase, Sean D. McElderry, Scott Hahn posted to manycore-os by walteryhli on 2009-10-29 16:37:49 as
	HASS: a scheduler for heterogeneous multicore systems [My Copy] SIGOPS Oper. Syst. Rev., Vol. 43, No. 2. (2009), pp. 66-75. by Daniel Shelepov, Juan Carlos Saez Alcaide, Stacey Jeffery, et al.Alexandra Fedorova, Nestor Perez, Zhi F. Huang, Sergey Blagodurov, Viren Kumar posted to manycore-os by walteryhli on 2009-10-29 16:15:40 as
	Carbon: architectural support for fine-grained parallelism on chip multiprocessors [My Copy] SIGARCH Comput. Archit. News In ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture, Vol. 35, No. 2. (2007), pp. 162-173. by Sanjeev Kumar, Christopher J. Hughes, Anthony Nguyen posted to manycore-os by walteryhli on 2009-10-29 16:10:13 as along with 2 people dschuff qiongcai
	Runtime Environment for Tera-scale Platforms [My Copy] Intel Technology Journal, Vol. 11, No. 03. (22 August 2007) by Bratin Saha, Ali-Reza Adl-Tabatabai, Richard L. Hudson, et al.Vijay Menon, Tatiana Shpeisman, Mohan Rajagopalan, Anwar Ghuloum, Eric Sprangle, Anwar Rohillah, Doug Carmean posted to manycore-os by walteryhli on 2009-10-29 16:01:09 as along with 1 person dominik-g
	Effect of increasing chip density on the evolution of computer architectures. [My Copy] IBM Journal of Research & Development, Vol. 46, No. 2/3. (2002) by Ravi Nair posted to transistors systems scaling integrated computer circuits architecture by walteryhli on 2009-09-16 17:38:20 as
	Integrated continuous-time filter design - an overview [My Copy] Solid-State Circuits, IEEE Journal of In Solid-State Circuits, IEEE Journal of, Vol. 29, No. 3. (1994), pp. 166-176. by Y. P. Tsividis posted to mixed-design-arch by walteryhli on 2009-09-01 13:47:44 as
	A System Level Energy Model and Energy-Quality Evaluation for Integrated Transceiver Front-Ends [My Copy] Very Large Scale Integration (VLSI) Systems, IEEE Transactions on In Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Vol. 15, No. 1. (2007), pp. 90-103. by Ye Li, B. Bakkaloglu, C. Chakrabarti posted to mixed-design-arch by walteryhli on 2009-08-31 16:11:30 as
	Optimal power and noise allocation for analog and digital sections of a low power radio receiver [My Copy] In ISLPED '08: Proceeding of the 13th international symposium on Low power electronics and design (2008), pp. 271-276. by Kannan A. Sankaragomathi, Manodipan Sahoo, Satyam Dwivedi, Bharadwaj S. Amrutur, Navakanta Bhat posted to mixed-design-arch by walteryhli on 2009-08-31 16:03:40 as
	Power estimation methods for analog circuits for architectural exploration of integrated systems [My Copy] Very Large Scale Integration (VLSI) Systems, IEEE Transactions on In Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Vol. 10, No. 2. (2002), pp. 155-162. by E. Lauwers, G. Gielen posted to mixed-design-arch by walteryhli on 2009-08-31 14:01:50 as
	CAD tools for embedded analogue circuits in mixed-signal integrated systems on chip [My Copy] Computers and Digital Techniques, IEE Proceedings - In Computers and Digital Techniques, IEE Proceedings -, Vol. 152, No. 3. (2005), pp. 317-332. by G. G. E. Gielen posted to mixed-design-arch by walteryhli on 2009-08-31 13:58:33 as
	Scaling of analog-to-digital converters into ultra-deep-submicron CMOS [My Copy] Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005 In Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005 (2005), pp. 375-382. by Y. Chiu, B. Nikolic, P. R. Gray posted to mixed-design-scaling by walteryhli on 2009-08-31 13:38:40 as
	Impact of CMOS Scaling on RF/Mixed-Signal Circuit Designs [My Copy] Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on In Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on (2006), pp. 1514-1517. by Mau-Chung F. Chang posted to mixed-design-scaling by walteryhli on 2009-08-31 13:37:36 as
	Visualizing potential parallelism in sequential programs [My Copy] In PACT '08: Proceedings of the 17th international conference on Parallel architectures and compilation techniques (2008), pp. 82-90. by Graham D. Price, John Giacomoni, Manish Vachharajani posted to visualization by walteryhli on 2009-08-30 15:44:14 as along with 1 person ama08r
	Visualizing application behavior on superscalar processors [My Copy] Information Visualization, 1999. (Info Vis '99) Proceedings. 1999 IEEE Symposium on In Information Visualization, 1999. (Info Vis '99) Proceedings. 1999 IEEE Symposium on (1999), pp. 10-17, 141. by C. Stolte, R. Bosch, P. Hanrahan, M. Rosenblum posted to visualization by walteryhli on 2009-08-30 15:41:00 as
	TraceVis: an execution trace visualization tool [My Copy] In Workshop on Modeling, Benchmarking and Simulation (2005) by James Roberts, Craig Zilles posted to visualization by walteryhli on 2009-08-30 15:39:37 as
	Performance simulation of an Alpha microprocessor [My Copy] Computer In Computer, Vol. 31, No. 5. (1998), pp. 50-58. by M. Reilly, J. Edmondson posted to visualization by walteryhli on 2009-08-30 15:26:01 as
	Performance analysis using pipeline visualization [My Copy] Performance Analysis of Systems and Software, 2001. ISPASS. 2001 IEEE International Symposium on In Performance Analysis of Systems and Software, 2001. ISPASS. 2001 IEEE International Symposium on (2001), pp. 18-21. by C. Weaver, K. C. Barr, E. Marsman, D. Ernst, T. Austin posted to visualization by walteryhli on 2009-08-30 15:06:09 as
	PipeRench: a reconfigurable architecture and compiler [My Copy] Computer In Computer, Vol. 33, No. 4. (2000), pp. 70-77. by S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, R. R. Taylor posted to data-level-parallelism by walteryhli on 2009-04-19 10:34:11 as
	RaPiD - Reconfigurable Pipelined Datapath [My Copy] In FPL '96: Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers (1996), pp. 126-135. by Carl Ebeling, Darren C. Cronquist, Paul Franklin posted to data-level-parallelism by walteryhli on 2009-04-19 10:15:57 as
	Cooperative Caching for Chip Multiprocessors [My Copy] Computer Architecture, 2006. ISCA '06. 33rd International Symposium on In Computer Architecture, 2006. ISCA '06. 33rd International Symposium on (2006), pp. 264-276. by Jichuan Chang, G. S. Sohi posted to dynamic-cache-partitioning by walteryhli on 2008-12-22 07:23:51 as along with 2 people Fantozzi adamx
	Organizing the Last Line of Defense before Hitting the Memory Wall for CMPs [My Copy] High-Performance Computer Architecture, International Symposium on, Vol. 0 (2004) by Chun Liu, Anand Sivasubramaniam, Mahmut Kandemir posted to dynamic-cache-partitioning by walteryhli on 2008-12-22 07:17:51 as along with 1 person Fantozzi
	An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors [My Copy] High Performance Computer Architecture, 2007. HPCA 2007. IEEE 13th International Symposium on In High Performance Computer Architecture, 2007. HPCA 2007. IEEE 13th International Symposium on (2007), pp. 2-12. by H. Dybdahl, P. Stenstrom posted to dynamic-cache-partitioning by walteryhli on 2008-12-22 07:13:33 as along with 3 people mengjuwu Fantozzi mamadoudiao
	MLP-Aware Dynamic Cache Partitioning [My Copy] Parallel Architecture and Compilation Techniques, 2007. PACT 2007. 16th International Conference on In Parallel Architecture and Compilation Techniques, 2007. PACT 2007. 16th International Conference on (2007), pp. 418-418. by M. Moreto, F. J. Cazorla, A. Ramirez, M. Valero posted to dynamic-cache-partitioning by walteryhli on 2008-12-22 07:06:34 as
	Reevaluating Amdahl's law [My Copy] Commun. ACM, Vol. 31, No. 5. (1988), pp. 532-533. by John L. Gustafson posted to amdahl-law-manycore by walteryhli on 2008-12-01 15:35:03 as along with 4 people kroatiker hubris mitake takeha-e
	Amdahls Law Revisited for Single Chip Systems [My Copy] International Journal of Parallel Programming, Vol. 35, No. 2. (April 2007), pp. 101-123. by Paul, Joann, Meyer, Brett posted to amdahl-law-manycore by walteryhli on 2008-12-01 15:31:05 as along with 1 person and 1 group sharshera SCAL
	Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors [My Copy] IEEE Comput. Archit. Lett., Vol. 5, No. 1. (2006) by Tomer Y. Morad, Uri C. Weiser, Avinoam Kolodny, Mateo Valero, Eduard Ayguade posted to amdahl-law-manycore by walteryhli on 2008-12-01 15:24:06 as
	Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors [My Copy] In MICRO 35: Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture (2002), pp. 383-394. by André Seznec, Eric Toullec, Olivier Rochecouste posted to area-estimation by walteryhli on 2008-11-30 15:18:38 as
	An area model for on-chip memories and its application [My Copy] Solid-State Circuits, IEEE Journal of In Solid-State Circuits, IEEE Journal of, Vol. 26, No. 2. (1991), pp. 98-106. by J. M. Mulder, N. T. Quach, M. J. Flynn posted to area-estimation by walteryhli on 2008-11-30 15:05:38 as
	Computer Architecture: A Quantitative Approach [My Copy] by John Hennessy, John L. Hennessy, David Goldberg, David A. Patterson posted to waterfall-execution-model by walteryhli on 2008-11-25 08:44:06 as along with 2 people and 1 group jmmcg mzabidi CompArch
	Recovery mechanism for latency misprediction [My Copy] Parallel Architectures and Compilation Techniques, 2001. Proceedings. 2001 International Conference on In Parallel Architectures and Compilation Techniques, 2001. Proceedings. 2001 International Conference on (2001), pp. 118-128. by E. Morancho, J. M. Llaberia, A. Olive posted to waterfall-execution-model by walteryhli on 2008-11-22 14:20:19 as
	XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in both Defective and Defect-free Interconnects [My Copy] Design and Diagnostics of Electronic Circuits and Systems, 2007. DDECS '07. IEEE In Design and Diagnostics of Electronic Circuits and Systems, 2007. DDECS '07. IEEE (2007), pp. 1-4. by A. K. Palit, K. K. Duganapalli, W. Arrheier posted to interconnect-crosstalk by walteryhli on 2008-11-17 15:23:31 as
	An RLC interconnect model based on fourier analysis [My Copy] Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on In Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 24, No. 2. (2005), pp. 170-183. by Guoqing Chen, E. G. Friedman posted to interconnect-crosstalk by walteryhli on 2008-11-17 15:20:52 as
	A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips [My Copy] In ATS '05: Proceedings of the 14th Asian Test Symposium on Asian Test Symposium (2005), pp. 22-27. by Ajoy K. Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Juergen Schloeffel posted to interconnect-crosstalk by walteryhli on 2008-11-17 15:11:35 as
	Crosstalk fault modeling in defective pair of interconnects [My Copy] Integration, the VLSI Journal, Vol. 41, No. 1. (January 2008), pp. 27-37. by A. Palit, K. Duganapalli, W. Anheier posted to interconnect-crosstalk by walteryhli on 2008-11-17 15:10:17 as
	An analytical delay model for RLC interconnects [My Copy] Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on In Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 16, No. 12. (1997), pp. 1507-1514. by A. B. Kahng, S. Muddu posted to interconnect-crosstalk by walteryhli on 2008-11-17 14:49:49 as
	Analysis of on-chip inductance effects for distributed RLC interconnects [My Copy] Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 21, No. 8. (2002), pp. 904-915. by K. Banerjee, A. Mehrotra posted to interconnect-crosstalk by walteryhli on 2008-11-17 14:37:21 as along with 1 person mobius2004

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data-level-parallelism	4
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soc-project-management	4
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