A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion Export

@article{Elmala:2006, abstract = {A linear Doherty amplifier is presented. The design reduces AM-PM distortion by optimizing the device-size ratio of the carrier and peak amplifiers to cancel each other's phase variation. Consequently, this design achieves both good linearity and high backed-off efficiency associated with the Doherty technique, making it suitable for systems with large peak-to-average power ratio (WLAN, WiMAX, etc.). The fully integrated design has on-chip quadrature hybrid coupler, impedance transformer, and output matching networks. The experimental 90-nm CMOS prototype operating at 3.65 GHz achieves 12.5\% power-added efficiency (PAE) at 6 dB back-off, while exceeding IEEE 802.11a -25 dB error vector magnitude (EVM) linearity requirement (using 1.55-V supply). A 28.9 dBm maximum Psat is achieved with 39\% PAE (using 1.85-V supply). The active die area is 1.2 mm².}, author = {Elmala, M. and Paramesh, J. and Soumyanath, K.}, citeulike-article-id = {6086698}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/JSSC.2006.874284}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1637597}, day = {30}, doi = {10.1109/JSSC.2006.874284}, journal = {Solid-State Circuits, IEEE Journal of}, keywords = {cmos, doherty, linearity, linearization, power-amplifier}, month = {May}, number = {6}, pages = {1323--1332}, posted-at = {2009-11-08 22:23:30}, priority = {2}, title = {A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion}, url = {http://dx.doi.org/10.1109/JSSC.2006.874284}, volume = {41}, year = {2006} }

TY - JOUR ID - Elmala:2006 L3 - citeulike-article-id:6086698 N2 - A linear Doherty amplifier is presented. The design reduces AM-PM distortion by optimizing the device-size ratio of the carrier and peak amplifiers to cancel each other's phase variation. Consequently, this design achieves both good linearity and high backed-off efficiency associated with the Doherty technique, making it suitable for systems with large peak-to-average power ratio (WLAN, WiMAX, etc.). The fully integrated design has on-chip quadrature hybrid coupler, impedance transformer, and output matching networks. The experimental 90-nm CMOS prototype operating at 3.65 GHz achieves 12.5% power-added efficiency (PAE) at 6 dB back-off, while exceeding IEEE 802.11a -25 dB error vector magnitude (EVM) linearity requirement (using 1.55-V supply). A 28.9 dBm maximum Psat is achieved with 39% PAE (using 1.85-V supply). The active die area is 1.2 mm². IS - 6 JF - Solid-State Circuits, IEEE Journal of EP - 1332 TI - A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion VL - 41 SP - 1323 KW - cmos KW - doherty KW - linearity KW - linearization KW - power-amplifier AU - Elmala, M AU - Paramesh, J AU - Soumyanath, K PY - 2006/05/30/ UR - http://dx.doi.org/10.1109/JSSC.2006.874284 ER -