A Ultra-High PAE Doherty Amplifier Basedon 0.13- <img src="/images/tex/241.gif" alt="μ"> m CMOS Process Export

@article{Kang:2006, abstract = {A 2.4-GHz Doherty CMOS power amplifier (PA) with ultra-high efficiency [power added efficiency (PAE)] is presented. A 0.13-mum standard CMOS process is employed and the two-stage circuit is configured for a 3.2-V operation. For a compact realization of the circuit, all matching circuits including a quarter wave transformer and input phase compensation transmission lines are implemented with lumped components. To modulate properly and maximize the PAE at P_{1 dB}, the input power of the class C peaking power cell is adjusted by optimizing the gate bias of the peaking driver cell. By doing so, the gain compression of the carrier cell is compensated by the gain expansion of the peaking cell up to the full power. This amplifier delivers a 22.7dBm of P₁ dB and 60\% of PAE with 25dB of power gain at 2.4 GHz. The PAE at 5 dB backed-off power level shows about 35\%. The excellent PAE of the circuit is the best data ever reported from linear CMOS PAs. The successful demonstration of the Doherty CMOS PA with lumped components is expected to be applied for a full-integration of the circuit}, author = {Kang, Jongchan and Yu, Daekyu and Min, Kyoungjoon and Kim, Bumman}, citeulike-article-id = {6086709}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/LMWC.2006.880703}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1683807}, day = {28}, doi = {10.1109/LMWC.2006.880703}, journal = {Microwave and Wireless Components Letters, IEEE}, keywords = {cmos, doherty, power-amplifier, rfic}, month = {August}, number = {9}, pages = {505--507}, posted-at = {2009-11-08 22:38:01}, priority = {2}, title = {A Ultra-High PAE Doherty Amplifier Basedon 0.13- <img src="/images/tex/241.gif" alt="\mu"> m CMOS Process}, url = {http://dx.doi.org/10.1109/LMWC.2006.880703}, volume = {16}, year = {2006} }

TY - JOUR ID - Kang:2006 L3 - citeulike-article-id:6086709 N2 - A 2.4-GHz Doherty CMOS power amplifier (PA) with ultra-high efficiency [power added efficiency (PAE)] is presented. A 0.13-mum standard CMOS process is employed and the two-stage circuit is configured for a 3.2-V operation. For a compact realization of the circuit, all matching circuits including a quarter wave transformer and input phase compensation transmission lines are implemented with lumped components. To modulate properly and maximize the PAE at P_{1 dB}, the input power of the class C peaking power cell is adjusted by optimizing the gate bias of the peaking driver cell. By doing so, the gain compression of the carrier cell is compensated by the gain expansion of the peaking cell up to the full power. This amplifier delivers a 22.7dBm of P₁ dB and 60% of PAE with 25dB of power gain at 2.4 GHz. The PAE at 5 dB backed-off power level shows about 35%. The excellent PAE of the circuit is the best data ever reported from linear CMOS PAs. The successful demonstration of the Doherty CMOS PA with lumped components is expected to be applied for a full-integration of the circuit IS - 9 JF - Microwave and Wireless Components Letters, IEEE EP - 507 TI - A Ultra-High PAE Doherty Amplifier Basedon 0.13- <img src="/images/tex/241.gif" alt="\mu"> m CMOS Process VL - 16 SP - 505 KW - cmos KW - doherty KW - power-amplifier KW - rfic AU - Kang, Jongchan AU - Yu, Daekyu AU - Min, Kyoungjoon AU - Kim, Bumman PY - 2006/08/28/ UR - http://dx.doi.org/10.1109/LMWC.2006.880703 ER -